Abstract: A memory device of embodiments includes: a semiconductor layer extending in a first direction; a gate electrode layer containing a first material or a second material, the first material containing tantalum (Ta), tungsten (W), and nitrogen (N), an atomic concentration of nitrogen being less than a sum of an atomic concentration of tantalum and an atomic concentration of tungsten, the second material containing niobium (Nb), molybdenum (Mo), and nitrogen (N), and an atomic concentration of nitrogen being less than a sum of an atomic concentration of niobium and an atomic concentration of molybdenum; a charge storage layer provided between the semiconductor layer and the gate electrode layer; a first insulating layer provided between the semiconductor layer and the charge storage layer; and a second insulating layer provided between the charge storage layer and the gate electrode layer.

Abstract: According to one embodiment, a semiconductor device includes a stacked body of alternating conductor layers and insulator layers stacked in a first direction and a columnar body extending through the stacked body in the first direction. The columnar body includes a first insulating layer extending in the first direction and comprising aluminum and oxygen, a semiconductor layer between the first insulating layer and the conductor layers of the stacked body, a charge storage film between the semiconductor layer and the conductor layers, and a second insulating layer between the semiconductor layer and the first insulating layer and comprising silicon and oxygen. An interface between the semiconductor layer and the second insulating layer contains nitrogen to eliminate defects which may reduce channel mobility or the like.

Abstract: A method for manufacturing an oxide film according to an embodiment includes forming a first film containing aluminum (Al) and nitrogen (N), and forming a second film containing aluminum (Al) and oxygen (O) by oxidizing the first film in an atmosphere containing heavy water (D2O).

Abstract: A memory device including a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.

Abstract: A semiconductor device manufacturing method of embodiments includes: forming an aluminum nitride film; forming an aluminum hydroxide film containing diaspore-type aluminum hydroxide by performing treatment in a fluid containing water to the aluminum nitride film; and forming an aluminum oxide film containing ?-type aluminum oxide by performing heat treatment to the aluminum hydroxide film at a temperature equal to or more than 500° C. and equal to or less than 800° C.

Abstract: A storage device includes a first electrode, a second electrode, and a resistance change storage layer between the first and second electrodes. The storage layer is either in a first resistance state or in a second resistance state having a resistance higher than the first resistance state and contains at least two elements selected from a group consisting of germanium, antimony, and tellurium. The storage device further includes an interface layer between the first electrode and the resistance change storage layer. The interface layer contains at least one of the elements of the resistance change storage layer and includes a conductive region and an insulating region.

Abstract: A semiconductor device of an embodiment includes a semiconductor layer, a gate electrode layer, and a first insulating layer provided between the semiconductor layer and the gate electrode layer, the first insulating layer including aluminum oxide including at least one crystal phase selected from the group consisting of alpha (?)-aluminum oxide and theta (?)-aluminum oxide, the first insulating layer having a thickness of equal to or less than 2.5 nm in a first direction from the semiconductor layer toward the gate electrode layer.

Abstract: A memory device according to an embodiment includes a semiconductor layer, a gate electrode layer, and a first dielectric layer provided between the semiconductor layer and the gate electrode layer. The first dielectric layer contains aluminum (Al), a first element, nitrogen (N), and silicon (Si). The first element is at least one element selected from the group consisting of scandium (Sc), yttrium (Y), lanthanoid (Ln), boron (B), gallium (Ga), and indium (In).

Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a charge storage layer between the semiconductor layer and the first gate electrode layer, the charge storage layer containing a first element, a second element, and oxygen, the first element being at least one element selected from the group consisting of hafnium and zirconium, and the second element being at least one element selected from the group consisting of nitrogen and aluminum; a first insulating layer between the charge storage layer and the first gate electrode layer; and a second insulating layer between the semiconductor layer and the first gate electrode layer, the second insulating layer containing silicon and nitrogen, the second insulating layer surrounding the charge storage layer in a cross section that being parallel to the first direction and including the charge storage layer.

Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.

Abstract: A semiconductor memory device of an embodiment includes: a semiconductor layer; a gate electrode layer; a first insulating layer provided between the semiconductor layer and the gate electrode layer; a second insulating layer provided between the first insulating layer and the gate electrode layer; and an intermediate layer provided between the first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number 61), a space group P42/nmc (space group number 137), or a space group R-3m (space group number 166), and the intermediate layer containing hafnium (Hf), oxygen (O), and nitrogen (N).

Abstract: According to one embodiment, a semiconductor memory device includes a stacked structure including conductive layers arranged in a first direction, and a columnar structure extending in the first direction in the first stacked structure. The columnar structure includes a semiconductor layer extending in the first direction, a charge storage layer between the semiconductor layer and the stacked structure, a first insulating layer between the semiconductor layer and the charge storage layer, and a second insulating layer between the stacked structure and the charge storage layer. The charge storage layer is aluminum nitride with a wurtzite crystal structure in which the c-axis is oriented in a direction towards the first insulating layer from the second insulating layer.

Abstract: A semiconductor memory device includes: a first and a second electrodes aligned in a first direction; a first semiconductor layer provided between the first and the second electrodes; a second semiconductor layer provided between the first semiconductor layer and the second electrode; a first charge accumulating layer provided between the first electrode and the first semiconductor layer; and a second charge accumulating layer provided between the second electrode and the second semiconductor layer. At least one of the first and the second charge accumulating layers include: a first and a second regions including nitrogen, aluminum, and oxygen and having different positions in a second direction; and a third region provided between the first and the second regions in the second direction. Oxygen is not included in the third region or a concentration of oxygen in the third region is lower than that in the first and the second regions.

Abstract: According to an embodiment, a memory device includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting with the first direction, an insulating layer provided between the first conductive layer and the second conductive layer, and a dielectric layer provided between the first conductive layer and the third conductive layer, and between the insulating layer and the third conductive layer, the dielectric layer having a first thickness thinner than a second thickness, the first thickness being a thickness between the first conductive layer and the third conductive layer, the second thickness being a thickness between the insulating layer and the third conductive layer, and the dielectric layer including an oxide including at least one of hafnium oxide and zirconium oxide.

Abstract: A semiconductor memory device of an embodiment includes: a semiconductor layer; a gate electrode layer; a first insulating layer provided between the semiconductor layer and the gate electrode layer; a second insulating layer provided between the first insulating layer and the gate electrode layer; and an intermediate layer provided between the first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number 61), a space group P42/nmc (space group number 137), or a space group R-3m (space group number 166), and the intermediate layer containing hafnium (Hf), oxygen (O), and nitrogen (N).

Abstract: A memory device of an embodiment includes: a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.

Abstract: According to an embodiment, a memory device includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting with the first direction, an insulating layer provided between the first conductive layer and the second conductive layer, and a dielectric layer provided between the first conductive layer and the third conductive layer, and between the insulating layer and the third conductive layer, the dielectric layer having a first thickness thinner than a second thickness, the first thickness being a thickness between the first conductive layer and the third conductive layer, the second thickness being a thickness between the insulating layer and the third conductive layer, and the dielectric layer including an oxide including at least one of hafnium oxide and zirconium oxide.

Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer, and a first layer provided between the first conductive layer and the second conductive layer and containing aluminum oxide that contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide is a ferroelectric.

Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive member, a first semiconductor member, and a first stacked member provided between the first conductive member and the first semiconductor member. The first stacked member includes a first insulating film, a second insulating film provided between the first insulating film and the first semiconductor member, first and second layers. The first layer includes aluminum and nitrogen and is provided between the first and second insulating films. A first thickness of the first layer along a first direction is 3 nm or less. The first direction is from the first semiconductor member toward the first conductive member. The second layer contacts the first layer, includes silicon and nitrogen, and is provided at one of a position between the first layer and the second insulating film or a position between the first layer and the first insulating film.