Patents by Inventor Tsunehiro Ino
Tsunehiro Ino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7795121Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0?x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.Type: GrantFiled: January 31, 2008Date of Patent: September 14, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Akio Kaneko, Nobutoshi Aoki
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Publication number: 20100078704Abstract: A semiconductor storage element includes: a source region and a drain region provided in a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate between the source region and the drain region; a charge storage film provided on the tunnel insulating film; a block insulating film provided on the charge storage film; a gate electrode provided on the block insulating film; and a region containing a gas molecule, the region provided in a neighborhood of an interface between the charge storage film and the block insulating film.Type: ApplicationFiled: March 16, 2009Publication date: April 1, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsunehiro Ino, Shosuke Fujii, Jun Fujiki, Akira Takashima, Masao Shingu, Daisuke Matsushita, Naoki Yasuda, Koichi Muraoka
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Patent number: 7655971Abstract: A nonvolatile semiconductor memory device includes: a source region and a drain region formed at a distance from each other in a semiconductor substrate; a tunnel insulating film formed on the semiconductor substrate between the source region and the drain region; a charge storage film formed on the tunnel insulating film; a first alumina layer formed on the charge storage film, and having a first impurity element added thereto, the first impurity element having an octacoordinate ion radius of 63 pm or greater, the first impurity element having a concentration distribution in a layer thickness direction of the first alumina layer that becomes the largest in a region close to the side of the charge storage film; a second alumina layer formed on the first alumina layer, and not having the first impurity element added thereto; and a control gate electrode formed on the second alumina layer.Type: GrantFiled: September 19, 2007Date of Patent: February 2, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Kouichi Muraoka
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Patent number: 7646072Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.Type: GrantFiled: January 22, 2009Date of Patent: January 12, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
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Patent number: 7629243Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0?x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.Type: GrantFiled: July 18, 2006Date of Patent: December 8, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Akio Kaneko, Nobutoshi Aoki
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Patent number: 7608849Abstract: The present invention provides a non-volatile switching element having a novel structure that operates at a high speed and enables high integration, and an integrated circuit that includes such non-volatile switching elements. The switching element includes: a switching film formed on a substrate, made of a material causing a 10 times or greater change in electric resistance with a temperature change within a range of ±80 K from a predetermined temperature; a Peltier element causing the switching film to have the temperature change; a heat conducting/electric insulating film provided between the switching film and the Peltier element, to conduct heat from the Peltier element; and a pair of electrodes connected to the switching film.Type: GrantFiled: October 31, 2006Date of Patent: October 27, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Masato Koyama
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Publication number: 20090242963Abstract: In a semiconductor device, the side walls are made of SiO2, SiN or SiON, and the top insulating film or gate insulating film is made of an oxide including Al, Si, and metal element M so that the number ratio Si/M is set to no less than a number ratio Si/M at a solid solubility limit of SiO2 composition in a composite oxide including metal element M and Al and set to no more than a number ratio Si/M at the condition that the dielectric constant is equal to the dielectric constant of Al2O3 and so that the number ratio Al/M is set to no less than a number ratio Al/M where the crystallization of an oxide of said metal element M is suppressed due to the Al element and set to no more than a number ratio Al/M where the crystallization of the Al2O3 is suppressed due to the metal element M.Type: ApplicationFiled: September 19, 2008Publication date: October 1, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Masao SHINGU, Shoko Kikuchi, Akira Takashima, Tsunehiro Ino, Koichi Muraoka
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Publication number: 20090212346Abstract: A semiconductor memory element includes: a tunnel insulating film formed on a semiconductor substrate; a HfON charge storage film with Bevan clusters formed on the tunnel insulating film; a blocking film formed on the HfON charge storage film; and a gate electrode formed on the blocking film.Type: ApplicationFiled: September 18, 2008Publication date: August 27, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro INO, Naoki Yasuda, Koichi Muraoka, Jun Fujiki, Shoko Kikuchi, Keiko Ariyoshi
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Publication number: 20090166767Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.Type: ApplicationFiled: January 22, 2009Publication date: July 2, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
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Publication number: 20090134479Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.Type: ApplicationFiled: January 22, 2009Publication date: May 28, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
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Publication number: 20090134480Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.Type: ApplicationFiled: January 22, 2009Publication date: May 28, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
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Publication number: 20090057753Abstract: A nonvolatile semiconductor memory device includes a source region and a drain region spaced from each other in a surface of a semiconductor layer, a tunnel insulating film provided on the semiconductor layer between the source region and the drain region, a charge storage film provided on the tunnel insulating film, a block insulating film provided on the charge storage film, and a control gate electrode provided on the block insulating film. The block insulating film is made of (Rm1?xLnx)2?yAlyO3+?, where Ln is one or more selected from Pr, Tb, Ce, Yb, Eu, and Sm, Rm is one or more selected from La, Nd, Gd, Dy, Ho, Er, Tm, Lu, Y, and Sc, 0<x<0.167 (but 0<x<0.333 if Ln is Pr, and 0<x<0.292 if Ln is Tb), 0.95?y?1.20, and 0???x(2?y)/2 (but ?x(2?y)/2???0 if Ln is Yb, Eu, and Sm, 0???x(2?y)/3 if Ln is Pr, and 0???3x(2?y)/14 if Ln is Tb).Type: ApplicationFiled: August 18, 2008Publication date: March 5, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tsunehiro INO
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Patent number: 7498643Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.Type: GrantFiled: March 13, 2006Date of Patent: March 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
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Publication number: 20080271990Abstract: A method of fabricating by co-sputtering deposition a lanthanoid aluminate film with enhanced electrical insulativity owing to suppression of deviation in composition of the film is disclosed. Firstly within a vacuum chamber, hold two separate targets, one of which is made of lanthanoid aluminate (LnAlO3) and the other of which is made of aluminum oxide (Al2O3). Then, transport and load a substrate into the vacuum chamber. Next, introduce a chosen sputtering gas into this chamber. Thereafter, perform sputtering of both the targets at a time to thereby form a lanthanoid aluminate film on the substrate surface. This film is well adaptable for use as ultra-thin high dielectric constant (high-k) gate dielectrics in highly miniaturized metal oxide semiconductor (MOS) transistors.Type: ApplicationFiled: December 28, 2007Publication date: November 6, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsunehiro Ino, Akira Takashima
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Publication number: 20080258264Abstract: Disclosed is a semiconductor device comprising a Ge semiconductor area, and an insulating film area, formed in direct contact with the Ge semiconductor area, containing metal, germanium, and oxygen.Type: ApplicationFiled: June 12, 2008Publication date: October 23, 2008Inventors: Yoshiki Kamata, Akira Nishiyama, Tsunehiro Ino, Yuuichi Kamimuta, Masahiro Koike
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Publication number: 20080146013Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0?x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.Type: ApplicationFiled: January 31, 2008Publication date: June 19, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Akio Kaneko, Nobutoshi Aoki
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Publication number: 20080116507Abstract: A nonvolatile semiconductor memory device includes: a source region and a drain region formed at a distance from each other in a semiconductor substrate; a tunnel insulating film formed on the semiconductor substrate between the source region and the drain region; a charge storage film formed on the tunnel insulating film; a first alumina layer formed on the charge storage film, and having a first impurity element added thereto, the first impurity element having an octacoordinate ion radius of 63 pm or greater, the first impurity element having a concentration distribution in a layer thickness direction of the first alumina layer that becomes the largest in a region close to the side of the charge storage film; a second alumina layer formed on the first alumina layer, and not having the first impurity element added thereto; and a control gate electrode formed on the second alumina layer.Type: ApplicationFiled: September 19, 2007Publication date: May 22, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro INO, Kouichi Muraoka
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Patent number: 7348644Abstract: Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film.Type: GrantFiled: April 20, 2006Date of Patent: March 25, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Koike, Masato Koyama, Tsunehiro Ino, Yuuichi Kamimuta, Akira Takashima, Masamichi Suzuki, Akira Nishiyama
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Patent number: 7300838Abstract: Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film.Type: GrantFiled: April 20, 2006Date of Patent: November 27, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Koike, Masato Koyama, Tsunehiro Ino, Yuuichi Kamimuta, Akira Takashima, Masamichi Suzuki, Akira Nishiyama
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Publication number: 20070252232Abstract: It is made possible to provide a semiconductor device and a method for manufacturing the semiconductor device that have the highest possible permittivity and can be produced at low production costs. A method for manufacturing a semiconductor device, includes: forming an amorphous film containing (HfzZr1-z)xSi1-xO2-y (0.81?x?0.99, 0.04?y?0.25, 0?z?1) on a semiconductor substrate, the ranges of composition ratios x, y, and z being values measured by XPS; and transforming the amorphous film into an insulating film containing (HfzZr1-z)xSi1-xO2 as tetragonal crystals, by performing annealing at 750° C. or higher on the amorphous film in an atmosphere containing oxygen.Type: ApplicationFiled: April 27, 2007Publication date: November 1, 2007Inventors: Tsunehiro Ino, Yasushi Nakasaki