Patents by Inventor Tsunehiro Nakajima

Tsunehiro Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140001487
    Abstract: A semiconductor device and its method of manufacture. In the method, a front surface element structure is formed on a front surface of a semiconductor wafer, for example an SiC wafer. Then, a supporting substrate is bonded to wafer's front surface through an adhesive. The wafer's rear surface is ground and polished to thin it, with the supporting substrate bonded to the wafer. Next a V groove passing through the SiC wafer and reaching the adhesive is formed in the wafer's rear surface, and the wafer is cut into individual chips. An electrode film is formed on the groove's side wall and the chip's rear surface and a Schottky junction is formed between a drift layer, which is the chip, and the film. Then, the film is annealed. A tape is attached to the wafer's rear surface which has been cut into the chips. Then, the supporting substrate peels off from the wafer.
    Type: Application
    Filed: September 13, 2011
    Publication date: January 2, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Tsunehiro Nakajima
  • Patent number: 8604584
    Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: December 10, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiroki Wakimoto, Kenichi Iguchi, Koh Yoshikawa, Tsunehiro Nakajima, Shunsuke Tanaka, Masaaki Ogino
  • Patent number: 8324044
    Abstract: A method of producing a semiconductor device that has a silicon substrate including a first major surface and a second major surface thereof, a front surface device structure being formed in a region of the first major surface, the method has a step of forming a rear electrode in a region of the second major surface, which includes evaporating or sputtering aluminum-silicon onto the second major surface to form an aluminum silicon film as a first layer of the rear electrode, the aluminum silicon film having a silicon concentration of at least 2 percent by weight when the thickness thereof is less than 0.3 ?m.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: December 4, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kenichi Kazama, Tsunehiro Nakajima, Koji Sasaki, Akio Shimizu, Takashi Hayashi, Hiroki Wakimoto
  • Publication number: 20110215435
    Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 8, 2011
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Hiroki WAKIMOTO, Kenichi Iguchi, Koh Yoshikawa, Tsunehiro Nakajima, Shunsuke Tanaka, Masaaki Ogino
  • Publication number: 20110121360
    Abstract: A semiconductor device includes a silicon substrate having a first major surface and a second major surface opposite to the first major surface, a drift layer and a collector layer formed in sequence in the silicon substrate from the first major surface, and an aluminum silicon film formed on the second major surface. The drift layer is of a first conductivity type, and is surrounded by a semiconductor layer of a second conductivity type including the collector layer.
    Type: Application
    Filed: December 17, 2010
    Publication date: May 26, 2011
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventors: Kenichi KAZAMA, Tsunehiro NAKAJIMA, Koji SASAKI, Akio SHIMIZU, Takashi HAYASHI, Hiroki WAKIMOTO
  • Publication number: 20110086471
    Abstract: A method of producing a semiconductor device that has a silicon substrate including a first major surface and a second major surface thereof, a front surface device structure being formed in a region of the first major surface, the method has a step of forming a rear electrode in a region of the second major surface, which includes evaporating or sputtering aluminum-silicon onto the second major surface to form an aluminum silicon film as a first layer of the rear electrode, the aluminum silicon film having a silicon concentration of at least 2 percent by weight when the thickness thereof is less than 0.3 ?m.
    Type: Application
    Filed: December 17, 2010
    Publication date: April 14, 2011
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventors: Kenichi KAZAMA, Tsunehiro Nakajima, Koji Sasaki, Akio Shimizu, Takashi Hayashi, Hiroki Wakimoto
  • Patent number: 7897452
    Abstract: A method of producing a semiconductor device having a thickness of 90 ?m to 200 ?m and with an electrode on the rear surface, which achieves a high proportion of non-defective devices by optimizing the silicon concentration and thickness of the aluminum-silicon electrode. A surface device structure is formed on a first major surface of a silicon substrate. A buffer layer and a collector layer are formed on the second major surface after grinding to reduce the thickness of the substrate. On the collector layer, a collector electrode is formed including a first layer of an aluminum-silicon film having a thickness of 0.3 ?m to 1.0 ?m and a silicon concentration of 0.5 percent to 2 percent by weight, preferably not more than 1 percent by weight.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: March 1, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Kenichi Kazama, Tsunehiro Nakajima, Koji Sasaki, Akio Shimizu, Takashi Hayashi, Hiroki Wakimoto
  • Publication number: 20070004098
    Abstract: A method of producing a semiconductor device having a thickness of 90 ?m to 200 ?m and with an electrode on the rear surface, which achieves a high proportion of non-defective devices by optimizing the silicon concentration and thickness of the aluminum-silicon electrode. A surface device structure is formed on a first major surface of a silicon substrate. A buffer layer and a collector layer are formed on the second major surface after grinding to reduce the thickness of the substrate. On the collector layer, a collector electrode is formed including a first layer of an aluminum-silicon film having a thickness of 0.3 ?m to 1.0 ?m and a silicon concentration of 0.5 percent to 2 percent by weight, preferably not more than 1 percent by weight.
    Type: Application
    Filed: June 16, 2006
    Publication date: January 4, 2007
    Inventors: Kenichi Kazama, Tsunehiro Nakajima, Koji Sasaki, Akio Shimizu, Takashi Hayashi, Hiroki Wakimoto