Patents by Inventor Tsuneo Nakata

Tsuneo Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7904085
    Abstract: A transmitter/receiver 101 on a mobile body 10 utilizes a plurality of antennas 100. It is assumed that a plurality of the antennas 100 are distributed and arranged in a moving direction of the mobile body, and the antennas at both ends are away from each other at an extent that a distance between the antennas is not negligible as compared with an interval of the base station. A radio wave from the base station 102-1 is stronger in intensity in 100-1 than in the center, and the radio wave from the base station 102-2 is stronger in intensity in 100-2 than in the center, respectively, whereby the communication stabilization effect, which is larger as compared with the case that the antennas are locally located in the center, is expected.
    Type: Grant
    Filed: February 21, 2005
    Date of Patent: March 8, 2011
    Assignee: NEC Corporation
    Inventors: Tsuneo Nakata, Akira Arutaki, Makoto Nishio
  • Publication number: 20110022881
    Abstract: A distributed resource managing system has one or more resource managing processes corresponding to each of predefined events that change the states of resources, on a communication network where each of a plurality of tasks can use a plurality of resources. Each of the one or more resource managing processes includes an assignor which, when it receives a request to protect any specific task against the event that changes states of resources to which its own process corresponds, assigns backup resources including a resource already selected by another resource managing process to the task in such a way that all tasks requested to be protected which use the resource can be protected from the event that changes the states of the resources, and an indicator which indicates information of the assigned backup resources to one or more recovery execution processes.
    Type: Application
    Filed: February 17, 2009
    Publication date: January 27, 2011
    Inventor: Tsuneo Nakata
  • Patent number: 7872998
    Abstract: An object of the present invention is to provide technology in which an HA is capable of efficiently maintaining registration information of an MR, and communication efficiency in registration/update processing between the HA and the MR is improved. A mobile node has a representative home address, a subsidiary home address, and a care-of address, and registers information (joint information) showing the relation between the representative home address, and all subsidiary home addresses, and the care-of address with the home agent, each time the mobile node moves to other network and is assigned a new care-of address.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: January 18, 2011
    Assignee: NEC Corporation
    Inventors: Masahiro Ono, Tsuneo Nakata, Morihisa Momona
  • Publication number: 20100332195
    Abstract: A design support apparatus includes a parameter set generation unit configured to obtain a plurality of types of parameters and sequentially generates parameter sets while sequentially changing each parameter, a design object shape data generation unit configured to generate design object shape data based on the parameter set and initial shape data representing an initial shape of the design object shape, a geometric penalty function value calculation unit configured to calculate a geometric penalty function value indicating suitability of geometric characteristics of the design object shape based on the design object shape data, an objective function calculation control unit configured to determine whether or not the parameter set is used to calculate an objective function based on the geometric penalty function value and an optimal value of the objective function, and an objective function calculation unit configured to calculate the objective function based on the parameter set.
    Type: Application
    Filed: June 25, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hitoshi YANAMI, Hirokazu Anai, Hidenao Iwane, Tsuneo Nakata
  • Patent number: 7844953
    Abstract: A program, an apparatus and a method verify a program that efficiently verifies a concurrent/parallel program, allowing interactively debugging the current/parallel program. The program causes a computer to execute a detection step that detects the function that has been altered and the function that uses a shared variable influenced by the alteration out of the program to be verified before and after the alteration and also detects the part that is influenced by the alteration, the control structure part and the other parts, a model generation step that generates a model on the basis of the outcome of the detection in the detection step and a verification step that verifies the program to be verified after the alteration by comparing the model of the program to be verified before the alteration and the model of the program to be verified after the alteration.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: November 30, 2010
    Assignee: Fujitsu Limited
    Inventors: Rafael Kazumiti Morizawa, Shinya Kuwamura, Tsuneo Nakata
  • Patent number: 7779377
    Abstract: A verification aiding apparatus includes an acquiring unit that acquires implementation description information of a verification target circuit, and a classifying unit that classifies registers in the verification target circuit for each type of processing for each command executable by the verification target circuit. Thus, implementation description classification information can be obtained. A setting unit performs a verification priority setting process and a generating unit performs a sequential command generating process, and a sequential command is output.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: August 17, 2010
    Assignee: Fujitsu Limited
    Inventor: Tsuneo Nakata
  • Publication number: 20100189112
    Abstract: Provided is a communication system in which a transmission path between communication nodes is multiplexed. A communication node transmitting packets decides the order of the packets to be transmitted through each transmission path on the assumption that an event that causes a state change to the transmission path occurs upon the start of the packet transmission, such that the packet reception order is not reversed at a communication node that receives the packets.
    Type: Application
    Filed: June 6, 2008
    Publication date: July 29, 2010
    Inventor: Tsuneo Nakata
  • Publication number: 20100172243
    Abstract: A scheduled transmission path of each packet to be transmitted is so determined that the order of predicted arrival time at a reception node is equal to the order of arrival time at a transmission node from estimate values of delay and velocity of each path. Only a packet predicted to arrive within the maximum permissible delay of each path is transmitted among the packets. This enables both of optimum allocation of the load between the paths and the prevention of a delay increase due to multiplexing.
    Type: Application
    Filed: March 27, 2007
    Publication date: July 8, 2010
    Inventor: Tsuneo Nakata
  • Patent number: 7752576
    Abstract: An input unit inputs specification description that includes a plurality of pieces of processing information each indicative of a processing performed by a design object and association information indicative of associations among the processing information. A node generating unit generates a node for each of the processing information. A link generating unit generates, based on the association information, a link that couples nodes generated by the node generating unit. A sub-chart generating unit configured to generate a plurality of sub-charts by dividing a chart indicating a content of the specification description, based on the node and the link. A function-module generating unit generates, for each of the sub-charts, a function module that executes a function based on the processing information corresponding to the node in the sub-chart and the association information corresponding to the link in the sub-chart.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: July 6, 2010
    Assignee: Fujitsu Limited
    Inventors: Qiang Zhu, Tsuneo Nakata
  • Publication number: 20100165863
    Abstract: A link band estimating apparatus includes packet transmitting means for transmitting a plurality of packets in succession via a route portion of a plurality of communication routes which share a link to be measured, packet interval measuring means for measuring an interval by which the packets are spaced apart in another route portion of the communication routes, and band calculating means for calculating the band of the link to be measured based on a value measured by the packet interval measuring means and a data size of the packets.
    Type: Application
    Filed: March 11, 2008
    Publication date: July 1, 2010
    Inventor: Tsuneo Nakata
  • Publication number: 20100169520
    Abstract: An information processor (program processing unit 1) for managing a data sequence in a fixed order comprises a direction array (reference data storage section 2) for storing a reference to each data item of the data sequence in an element of the index associated with the key to the data, and means (CPU 3) for changing all data keys referenced by elements within an arbitrary range of indexes in the direction array by the same amount, where memory contents within the range of the direction array are shifted by the number of indexes corresponding to the changed amount.
    Type: Application
    Filed: May 29, 2008
    Publication date: July 1, 2010
    Inventor: Tsuneo Nakata
  • Publication number: 20100153074
    Abstract: A design support apparatus for determining a plurality of objective functions for modeling an object having a plurality of elements, each of the elements providing variable geometrical parameters, the design support apparatus includes a memory for storing the variable geometrical parameters and a processor for executing a process including: determining boundary information associated with specified geometrical parameters of the elements which indicate a state of contact between the elements, dividing the variable geometrical parameters into a plurality of groups on the basis of the boundary information, and determining the plurality of objective functions for each of the groups by using the variable geometrical parameters.
    Type: Application
    Filed: December 1, 2009
    Publication date: June 17, 2010
    Applicant: Fujitsu Limited
    Inventors: Hitoshi YANAMI, Hirokazu Anai, Tsuneo Nakata, Hidenao Iwane
  • Publication number: 20100046520
    Abstract: A packet recovery method of the present invention is a packet recovery method upon loss of a plurality of packets transmitted from a first node 111 to second node 112 through a network in the order of sequence numbers assigned to each of said packets, wherein second node 112, upon detection of a loss of a packet transmitted from first node 111, transmits an acknowledgement message, including a sequence number of a packet whose receipt has been confirmed or whose loss has been detected and including information on the lost packet, to first node 111 through the network.
    Type: Application
    Filed: September 4, 2007
    Publication date: February 25, 2010
    Inventor: Tsuneo Nakata
  • Publication number: 20090287965
    Abstract: A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
    Type: Application
    Filed: January 23, 2009
    Publication date: November 19, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Ryosuke Oishi, Akio Matsuda, Koichiro Takayama, Tsuneo Nakata
  • Publication number: 20090276740
    Abstract: In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.
    Type: Application
    Filed: December 15, 2008
    Publication date: November 5, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Akio Matsuda, Ryosuke Oishi, Koichiro Takayama, Tsuneo Nakata, Rafael Kazumiti Morizawa
  • Publication number: 20090190493
    Abstract: In the prior art, in a case of measuring a speed of a narrow-bandwidth path of which the state fluctuates dynamically, a serious influence is placed upon a speed calculation with a sufficient precision, and a performance. Embedding probe information into a data packet, being actual data, to transfer two at a time allows the data packet having the probe information embedded to act as a probe packet of the packet pair technique as well. Further, in a system including a plurality of the paths, the data packets are distributed to the path two packets by two packets.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 30, 2009
    Inventor: Tsuneo Nakata
  • Publication number: 20090182539
    Abstract: An objective function can be mathematically approximated using a prescribed number of sample sets of design parameters and sets of a plurality of objective functions computed corresponding to them. A logical expression indicating a relation between or among arbitrary two or three objective functions of the plurality of mathematically approximated objective functions is computed as an inter-objective-function logical expression and a region that the arbitrary objective function values can take is displayed as a feasible region in an objective space corresponding to the arbitrary objective functions. Furthermore, a point or area in a design space corresponding to arbitrary design parameters corresponding to a point or area specified by a user in the displayed feasible region is displayed.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hirokazu Anai, Hitoshi Yanami, Tsuneo Nakata
  • Publication number: 20090182538
    Abstract: A unit 101 calculates a plurality of sets of objective functions of sample sets of input parameters. A unit 102 approximates the objective functions using a polynomial on the basis of the calculation result of the unit 101. A unit 103 calculates a logical expression indicating a logical relation between arbitrary two or three objective functions, of the plurality of mathematically approximated objective functions as an inter-objective function logical expression by a QE method. A unit 104 displays areas that the values of the objective functions can take as usable areas according to the inter-objective function logical expression. Units 105 and 106 determine an optimum set of design parameters by limiting the sets of design parameters to corresponding sets of design parameters in the neighborhood of a Pareto boundary on the basis of the Pareto boundary of an objective function recognized from the usable areas displayed.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hitoshi Yanami, Hirokazu Anai, Tsuneo Nakata, Naozumi Tsuda
  • Publication number: 20090059958
    Abstract: The task of the present invention is to reduce a load caused by a transmission of control information related to data packets and enhance a communication efficiency. In the present invention, when packets are transferred from a transferring node 101 to a transferring node 102, control information stored in each of data packets 301 is compiled together into a leader packet 302 located in the front position of a packet block 300-1, and then, transmitted from the transferring node 101 to the transferring node 102. When receiving this packet block 300-1, the transferring node 102 controls, based on the received control information in the leader packet, the transmission of the packets to be transferred to the transferring node 101.
    Type: Application
    Filed: January 18, 2007
    Publication date: March 5, 2009
    Applicant: NEC CORPORATION
    Inventor: Tsuneo Nakata
  • Publication number: 20080312890
    Abstract: Conditions necessary to be satisfied for execution of each use case from a use case description indicative of a requirements specification of the design object are acquired. Then a state satisfying the conditions, from among a set of states represented in a finite state machine model indicative of a design specification of the design object are detected. A presence or absence of an undetected state in the set of states in accordance with the detection is determined and output.
    Type: Application
    Filed: June 10, 2008
    Publication date: December 18, 2008
    Applicant: Fujitsu Limited
    Inventors: Qiang ZHU, Hiroaki Iwashita, Koichiro Takayama, Tsuneo Nakata