Patents by Inventor Tsuneo Nakata
Tsuneo Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080312881Abstract: A single module includes a shared combinational circuit, a multiplexed sequential circuit, and a common I/F and is substituted for a multiplexed module formed of plural modules of an identical category and type and including plural CPUs. Specifically, the shared combinational circuit is substituted for n combinational circuits, the multiplexed sequential circuit is substituted for n sequential circuits, and the common I/F is substituted for n input pins and n output pins.Type: ApplicationFiled: March 19, 2008Publication date: December 18, 2008Applicant: FUJITSU LIMITEDInventors: Yuzi Kanazawa, Takahide Yoshikawa, Tsuneo Nakata
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Publication number: 20080232390Abstract: A communication system including first, second, and third nodes interconnected via interconnect links, a primary path composed of an interconnect link between the first node and the third node, and a secondary path composed of an interconnect link between the first and second nodes and an interconnect link between the second and third nodes, wherein when the first node and the third node function as a transmitting node and a receiving node respectively, having a path multiplexing function to communicate with each other using bandwidths of a plurality of paths simultaneously, the first node transmits, to the second node, a path multiplexing request message for requesting communication with the third node, and when receiving the path multiplexing request message, the second node functions as a relay node and determines whether the primary path and the secondary path can be logically multiplexed by providing, to the first node, the bandwidth of the interconnect link between the second and third nodes, and if patType: ApplicationFiled: March 14, 2008Publication date: September 25, 2008Applicant: NEC CORPORATIONInventor: TSUNEO NAKATA
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Publication number: 20080126768Abstract: A verification aiding apparatus includes an acquiring unit that acquires implementation description information of a verification target circuit, and a classifying unit that classifies registers in the verification target circuit for each type of processing for each command executable by the verification target circuit. Thus, implementation description classification information can be obtained. A setting unit performs a verification priority setting process and a generating unit performs a sequential command generating process, and a sequential command is output.Type: ApplicationFiled: January 29, 2007Publication date: May 29, 2008Applicant: FUJITSU LIMITEDInventor: Tsuneo Nakata
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Publication number: 20080039015Abstract: A transmitter/receiver 101 on a mobile body 10 utilizes a plurality of antennas 100. It is assumed that a plurality of the antennas 100 are distributed and arranged in a moving direction of the mobile body, and the antennas at both ends are away from each other at an extent that a distance between the antennas is not negligible as compared with an interval of the base station. A radio wave from the base station 102-1 is stronger in intensity in 100-1 than in the center, and the radio wave from the base station 102-2 is stronger in intensity in 100-2 than in the center, respectively, whereby the communication stabilization effect, which is larger as compared with the case that the antennas are locally located in the center, is expected.Type: ApplicationFiled: February 21, 2005Publication date: February 14, 2008Inventors: Tsuneo Nakata, Akira Arutaki, Makoto Nishio
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Patent number: 7289450Abstract: A method for establishing a communications path between a source node and destination node. The method includes defining a first group of network elements (NEs) suitable for use in the communications path, contemporaneously determining available resources within each of the NEs of the first group of NEs, and contemporaneously reserving those available resources appropriate to establish the communications path. The reserved resources sufficient to establish the communications path are selected, while those reserved resources not selected are released. In the absence of available resources sufficient to establish the communications path, the method is repeated using a second group of NEs suitable for establishing the communications path.Type: GrantFiled: June 25, 2002Date of Patent: October 30, 2007Assignee: Lucent Technologies Inc.Inventor: Tsuneo Nakata
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Publication number: 20070195710Abstract: In allocating a resource circuit by circuit, a reference is made to a table signifying a one-versus-many correspondence between a subscriber and a circuit, thereby to reflect a state of the other circuit that an identical subscriber holds into the above resource allocation. As a rule, the table is dynamically updated, responding to a new circuit request by the subscriber holding a plurality of terminal apparatuses and a change in a network situation such as a load. This enables setting/observation of service conditions to be realized subscriber by subscriber in a subscriber network in which one subscriber occupies a plurality of the circuits. Further, this allows the occupied circuit number a subscriber not to be limited to the number of the circuit that is packaged onto one terminal.Type: ApplicationFiled: February 21, 2005Publication date: August 23, 2007Applicant: NEC CorporationInventor: Tsuneo Nakata
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Publication number: 20070036115Abstract: An object of the present invention is to provide technology in which an HA is capable of efficiently maintaining registration information of an MR, and communication efficiency in registration/update processing between the HA and the MR is improved. A mobile node has a representative home address, a subsidiary home address, and a care-of address, and registers information (joint information) showing the relation between the representative home address, and all subsidiary home addresses, and the care-of address with the home agent, each time the mobile node moves to other network and is assigned a new care-of address.Type: ApplicationFiled: September 15, 2004Publication date: February 15, 2007Inventors: Masahiro Ono, Tsuneo Nakata, Morihisa Momona
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Publication number: 20070022325Abstract: A program, an apparatus and a method verify a program that efficiently verifies a concurrent/parallel program, allowing interactively debugging the current/parallel program. The program causes a computer to execute a detection step that detects the function that has been altered and the function that uses a shared variable influenced by the alteration out of the program to be verified before and after the alteration and also detects the part that is influenced by the alteration, the control structure part and the other parts, a model generation step that generates a model on the basis of the outcome of the detection in the detection step and a verification step that verifies the program to be verified after the alteration by comparing the model of the program to be verified before the alteration and the model of the program to be verified after the alteration.Type: ApplicationFiled: September 29, 2005Publication date: January 25, 2007Applicant: FUJITSU LIMITEDInventors: Rafael Morizawa, Shinya Kuwamura, Tsuneo Nakata
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Publication number: 20070002748Abstract: When path status information is updated, the time at which the update is effective is recorded. A packet arrival time in each path is predicted based on new status information and data transmission history after the effective time. The packet is transmitted to the path that provides a fastest packet arrival time. This reflects the path status available from the reception side on the data transmitted in past, so that an actual data arrival time, an arrival time close to a reception completion time, or a reception completion time can be predicted.Type: ApplicationFiled: January 7, 2005Publication date: January 4, 2007Inventors: Tsuneo Nakata, Yuusuke Noguchi
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Publication number: 20060265676Abstract: An apparatus for verifying a specification includes a use-case extracting unit, a first setting unit, an operation extracting unit, a second setting unit, and a determining unit. The use-case extracting unit extracts an unprocessed use case from specification data. The first setting unit sets a condition based on a precondition, a postcondition, and an invariant condition for the use case. The operation extracting unit selects an event flow of an unprocessed path from the specification data and extracts an unprocessed operation (description) from the event flow selected. The second setting unit sets a precondition and a postcondition for the operation based on the extracted operation (description). The determining unit determines whether the invariant condition is valid.Type: ApplicationFiled: August 31, 2005Publication date: November 23, 2006Applicant: FUJITSU LIMITEDInventors: Qiang Zhu, Ryosuke Oishi, Tsuneo Nakata
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Publication number: 20060256803Abstract: A first identifier for identifying each flow belonging to a first group relating to a sequencing, a first sequential number, said first sequential number being unique within each flow of the first group flow, a second identifier for identifying a flow relating to a retransmitting control, and a second sequential number, said second sequential number being unique within each flow belonging to the second group flow, are affixed to a transmission packet to transmit it. A receiving node makes a request for retransmission based upon the second identifier and the second sequential number, and a transmitting node retransmits its packet. Also, in the sequencing of the packets, the receiving node takes a sequencing of the packet based upon the first identifier and the first sequential number.Type: ApplicationFiled: January 7, 2005Publication date: November 16, 2006Inventors: Tsuneo Nakata, Masahiro Ono
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Publication number: 20060236289Abstract: An input unit inputs specification description that includes a plurality of pieces of processing information each indicative of a processing performed by a design object and association information indicative of associations among the processing information. A node generating unit generates a node for each of the processing information. A link generating unit generates, based on the association information, a link that couples nodes generated by the node generating unit. A sub-chart generating unit configured to generate a plurality of sub-charts by dividing a chart indicating a content of the specification description, based on the node and the link. A function-module generating unit generates, for each of the sub-charts, a function module that executes a function based on the processing information corresponding to the node in the sub-chart and the association information corresponding to the link in the sub-chart.Type: ApplicationFiled: March 31, 2006Publication date: October 19, 2006Applicant: FUJITSU LIMITEDInventors: Qiang Zhu, Tsuneo Nakata
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Publication number: 20060182128Abstract: The present invention provides a data communication technology which is capable of securing flexibly a bandwidth for a traffic that is generated and which enables effective use of access lines or wireless resource. A mobile router uses a plurality of communication means, retains a plurality of narrow band communication routes for communicating with the home agent, and configures a broad band communication route by using the plurality of the narrow band communication routes as a single logical communication route. This enables a bandwidth to be flexibly secured in accordance with the traffic which is generated in the mobile network. In this case, the home agent is enabled to effectively use the access lines by referring to the route information so as to determine the destination address. Furthermore, it is possible to save the wireless resource under the initiative of the user by dynamically connecting to an alternative line or disconnecting a line which is being used in response to a request of the user.Type: ApplicationFiled: May 21, 2004Publication date: August 17, 2006Inventors: Tsuneo Nakata, Nasahiro Ono, Morihisa Momona, Kazuhiro Okanoue
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Patent number: 6829216Abstract: A method and system for designing a network includes generating a representation of a candidate network. The representation includes vertices and edges, where each vertex represents a path and each edge couples at least two vertices representing paths of which at most one path can be included in a network. A set of a maximum number of vertices, where no two vertices are coupled by an edge, is determined. The paths represented by the vertices of the set are included in the network.Type: GrantFiled: August 18, 2000Date of Patent: December 7, 2004Assignee: Hitachi Telecom (U.S.A.), Inc.Inventor: Tsuneo Nakata
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Publication number: 20030235154Abstract: A method for establishing a communications path between a source node and destination node. The method includes defining a first group of network elements (NEs) suitable for use in the communications path, contemporaneously determining available resources within each of the NEs of the first group of NEs, and contemporaneously reserving those available resources appropriate to establish the communications path. The reserved resources sufficient to establish the communications path are selected, while those reserved resources not selected are released. In the absence of available resources sufficient to establish the communications path, the method is repeated using a second group of NEs suitable for establishing the communications path.Type: ApplicationFiled: June 25, 2002Publication date: December 25, 2003Applicant: LUCENT TECHNOLOGIES INC.Inventor: Tsuneo Nakata
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Publication number: 20030115554Abstract: Information of definitions on interface specifications capable of expressing parallel behaviors is stored in a computer-readable storage medium while amounts of information are reduced. The present invention comprises: a first identifier region for storing, as a first set of ports, combination patterns of signal values that respective ports of a first set of ports are capable of assuming; a second identifier region for storing, as a second set of ports, combination patterns of signal values that respective ports of a second set of ports are capable of assuming; and a third identifier region for storing, as a third set of ports, functions of a circuit module defined as combinations of first identifiers and second identifiers, wherein the third identifiers include codes (par) indicating that starting order of combination patterns corresponding to the first identifiers and combination patterns corresponding to the second identifiers are undefined.Type: ApplicationFiled: November 18, 2002Publication date: June 19, 2003Applicant: Hitachi, Ltd.Inventors: Koji Ara, Kei Suzuki, Tsuneo Nakata, Hiroaki Iwashita, Satoshi Kowatari
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Patent number: 6452934Abstract: In a communication network having a plurality of terminals, such as packet forwarding apparatus, and a transport network which provides a connection between the terminals, when the transport network performs a state transition associated with a brief disconnection, a brief disconnection begin notification signal is sent to a terminal prior to a state transition operation and a brief disconnection end notification signal is sent to the terminal after the state transition operation. The terminal reroutes communication data to a storage or a redundant transport route during the period between the receipt of the brief disconnection begin notification and the receipt of the brief disconnection end notification. Accordingly, the communication data loss due to the brief disconnection between terminals associated with the state transition of the transport network can be reduced or eliminated.Type: GrantFiled: September 14, 1999Date of Patent: September 17, 2002Assignee: Hitachi, Ltd.Inventor: Tsuneo Nakata
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Patent number: 6141633Abstract: A verification apparatus which verifies whether or not a finite state machine indicating the operation of a synchronous sequential machine satisfies the property indicating the functional specification repeats the image computation in the M and the computation of a set product by q starting with the state set p when the finite state machine M, the subset q of the state of the M, and the subset p of the q are given; and checks the relation of the state set of the computation process. As a result, it can be determined, starting with a certain state in the p, whether or not a state transition path which eternally does not exceed the q exists.Type: GrantFiled: February 26, 1998Date of Patent: October 31, 2000Assignee: Fujitsu LimitedInventors: Hiroaki Iwashita, Tsuneo Nakata
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Patent number: 5708594Abstract: First, an initial operation model M.sub.0 of a pipeline is configured according to the pipeline configuration of a processor and the specification information about an instruction executed by the processor. Then, the number of the states of the initial operation model M.sub.0 is minimized to configure an operation model M. Based on the operation model M and a test state set H, listed are test instruction strings for the process in which the state of the operation model M indicates a transition from a predetermined input state to any of the test states contained in the test state set H without an occurrence of a conflict in the operation model M. A next time state, reached after the state of the operation model M has reached the test state of the test instruction string, is calculated and the next time state is input as a new input state to a test instruction string listing unit.Type: GrantFiled: May 3, 1995Date of Patent: January 13, 1998Assignee: Fujitsu LimitedInventors: Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose
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Patent number: 5588008Abstract: A method for generating a test pattern for use with a scan circuit utilized in detecting a degenerative failure in a synchronous sequential circuit including a memory element unit, having a scan register, and a combination circuit unit for receiving an external input and inputting a value from the memory element unit, and for supplying an external output and outputting a value to the memory element unit. The method includes generating, for an undetected failure, a test pattern for use in a combinational circuit. The method also includes generating a test pattern series for detecting a different failure by observing its external output value and by changing the external input value with the value set in a scan register of the memory element unit.Type: GrantFiled: October 26, 1992Date of Patent: December 24, 1996Assignee: Fujitsu LimitedInventor: Tsuneo Nakata