Abstract: A semiconductor device includes a non-conductive gate feature over a substrate and a spacer adjoining each sidewall of the non-conductive gate feature.

Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features in an inter-layer dielectric (ILD) over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. Source/drain (S/D) features are formed at edges of the active gate features in the substrate for forming transistor devices. The disclosed method provides an improved method for reducing parasitic capacitance among the transistor devices. In an embodiment, the improved formation method is achieved by introducing species into the dummy gate feature to increase the resistance of the dummy gate feature.

Abstract: A method of fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. In at least one embodiment, a non-conductive material is used for forming the dummy gate feature to replace a sacrificial gate electrode.

Abstract: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.

Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features in an inter-layer dielectric (ILD) over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. Source/drain (S/D) features are formed at edges of the active gate features in the substrate for forming transistor devices. The disclosed method provides an improved method for reducing parasitic capacitance among the transistor devices. In an embodiment, the improved formation method is achieved by introducing species into the dummy gate feature to increase the resistance of the dummy gate feature.

Abstract: A method of fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. In at least one embodiment, a non-conductive material is used for forming the dummy gate feature to replace a sacrificial gate electrode.

Abstract: Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion.

Abstract: A continuous and integrated cleaning/preparation process is described to condition a silicon surface for the formation of a high quality ultra thin gate oxide described. The process is conducted with the wafer surface immersed in an aqueous solution the composition of which is varied continuously according to the steps of the process. The process includes the initial removal of contaminants and particulates followed by the removal of a native oxide. Next the silicon surface is dressed in the present of both HF and ozone by removing a thin surface layer. Any interfacial contamination or surface structural defects which lay under the native oxide are thereby removed. Next a high quality chemical oxide is grown by the action of the ozone in the aqueous bath. The chemical oxide is found to be of higher purity and structural quality than native oxide and provides a superior passivation of the active surface prior to gate oxidation.

Abstract: An electrostatic charge-free solvent-type dryer for drying semiconductor wafers after a wet bench process is disclosed in a preferred embodiment and in an alternate embodiment. In the preferred embodiment, the electrostatic charge-free solvent-type dryer is constructed by a tank body, a wafer carrier, an elevator means, a tank cover and a conduit for feeding the flow of solvent vapor. At least one of the tank cover, the conduit for feeding the flow of solvent vapor and the plurality of partition plates is fabricated of a non-electrostatic material such that electrostatic charge is not generated in the flow of solvent vapor. In the alternate embodiment, a deionizer is further provided in the tank cavity for producing a flux of positive ions to neutralize any negative ions that are possibly produced in the flow of solvent vapor.

Abstract: A moisture-controlled wafer storage container for storing semiconductor wafers during processing and a method for using the container are provided. The container may be constructed of a container body that has a front wall, a back wall, a left-side wall, a right-side wall and a top wall defining a cavity therein for receiving a wafer cassette and wafers stored in the cassette. The cavity is further defined by a bottom wall of a wafer cassette when the cassette is positioned in the container to form a sealed cavity. The container further includes a moisture-absorbing means that is placed in the container or in fluid communication with the sealed cavity of the container for absorbing moisture and for controlling a relative humidity in the sealed cavity to less than 30%, and preferably to less than 20%, and more preferably to less than 10%.

Abstract: An electrostatic charge-free solvent-type dryer for drying semiconductor wafers after a wet bench process is disclosed in a preferred embodiment and in an alternate embodiment. In the preferred embodiment, the electrostatic charge-free solvent-type dryer is constructed by a tank body, a wafer carrier, an elevator means, a tank cover and a conduit for feeding the flow of solvent vapor. At least one of the tank cover, the conduit for feeding the flow of solvent vapor and the plurality of partition plates is fabricated of a non-electrostatic material such that electrostatic charge is not generated in the flow of solvent vapor. In the alternate embodiment, a deionizer is further provided in the tank cavity for producing a flux of positive ions to neutralize any negative ions that are possibly produced in the flow of solvent vapor.

Abstract: A wafer support for supporting and rotating a semiconductor wafer within a rapid thermal process chamber is formed of a single member of unitary construction. The unitary member includes a first, horizontal section for supporting the periphery of the wafer thereon, and a downwardly extending cylindrical section that is mounted for rotation within the chamber. The first and second sections are integrally formed to prevent radiant energy from passing there between and comprise materials that cause the support to act as a black body, yielding more uniform heating of the wafer. A recess formed in the horizontal section receives the outer edge of the wafer and prevents radiant heat from passing between the wafer and the support in those cases where the wafer is warped.

Abstract: An apparatus and a method for reducing solvent residue in a solvent-type dryer for drying semiconductor wafers have been disclosed. The apparatus is constructed by a tank body, a wafer carrier, an elevator means, a tank cover, a solvent vapor conduit and an exhaust means. The exhaust means is provided for fluid communication with a compartment in the tank cover such that any residual solvent vapor or any organic residue in the compartment left from the wafer drying cycle can be evacuated to a factory exhaust system. The present invention novel method for reducing solvent or organic residue in the dryer can be carried out, after the removal of the dried wafers from the dryer, by evacuating the compartment in the tank cover for a time period of between about 30 sec. and about 300 sec. until all residual solvent vapor or organic residue is evacuated.

Abstract: A wafer support for supporting and rotating a semiconductor wafer within a rapid thermal process chamber is formed of a single member of unitary construction. The unitary member includes a first, horizontal section for supporting the periphery of the wafer thereon, and a downwardly extending cylindrical section that is mounted for rotation within the chamber. The first and second sections are integrally formed to prevent radiant energy from passing there between and comprise materials that cause the support to act as a black body, yielding more uniform heating of the wafer. A recess formed in the horizontal section receives the outer edge of the wafer and prevents radiant heat from passing between the wafer and the support in those cases where the wafer is warped.