Abstract: An exemplary method for reading data stored in a flash memory includes: controlling the flash memory to perform a plurality of read operations upon each of a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from each of the memory cells as one of the bit sequences by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A method for enhancing error correction capability of a controller of a memory device without need to increase a basic error correction bit count of an Error Correction Code (ECC) engine includes: according to an error correction magnification factor, respectively obtaining a plurality of portions of data, where the portions are partial data to be encoded/decoded; and regarding the portions that are the partial data to be encoded/decoded, respectively performing encoding/decoding corresponding to the error correction magnification factor, in order to generate encoded/decoded data corresponding to a predetermined error correction bit count, where a ratio of the predetermined error correction bit count to the basic error correction bit count is equal to the error correction magnification factor. An associated memory device and the controller thereof are further provided.

Abstract: A method for performing data shaping is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a Trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data. An associated memory device and a controller thereof are also provided.

Abstract: The invention provides a data read method. First, a training sequence stored in a storage unit of a memory is read according to at least one sense voltage to obtain a read-out training sequence. Whether the read-out training sequence is correct is then determined. When the read-out training sequence is not correct, the sense voltage is adjusted.

Abstract: A flash memory device includes a flash memory and a controller. The flash memory includes a single level memory module and a multi level memory module. The single level memory module includes a first data bus and at least one single level cell flash memory. Each memory cell of the single level cell flash memory stores one bit of data. The multi level memory module includes a second data bus and at least one multi level cell flash memory. Each memory cell of the multi level cell flash memory stores more than one bit of data. The first data bus is coupled to the second data bus. During a write operation, the controller writes data to the single level memory module, and the single level memory module further transmits the data to the multi level memory module through the first and second data buses coupled therebetween without passing the data through the controller.

Abstract: A controlling method utilized in a flash memory device includes: compressing first data received from a host to generate second data; generating record data according to the first data and the second data where the record data records error correct coding (ECC) control information at least; executing ECC protection upon specific data selected from the first and second data to generate third data; and writing the third data into the flash memory device.

Abstract: A method for performing data shaping is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: according to contents of data to be written into or read from the Flash memory, generating/recovering an input seed of at least one randomizer/derandomizer; and utilizing the randomizer/derandomizer to generate a random function according to the input seed, for use of adjusting a plurality of bits of the data bit by bit. An associated memory device and a controller thereof are also provided.

Abstract: A method for performing memory access management includes: with regard to a same memory cell of a memory, according to a first digital value output by the memory, requesting the memory to output at least one second digital value, wherein the first digital value and the at least one second digital value are utilized for determining information of a same bit stored in the memory cell, and a number of various possible states of the memory cell is equal to a number of various possible combinations of all bit(s) stored in the memory cell; and based upon the at least one second digital value, generating/obtaining soft information of the memory cell, for use of performing soft decoding. An associated memory device and a controller thereof are also provided.

Abstract: A method for enhancing error correction capability of a controller of a memory device without increasing an Error Correction Code (ECC) engine encoding/decoding bit count includes: regarding a plurality of rows of a data bit array, respectively calculating a plurality of first parity codes; regarding a plurality of sets of columns of the data bit array, respectively calculating a plurality of second parity codes, wherein each set of the sets includes two or more of the columns, and the sets do not overlap; and performing encoding/decoding corresponding to the first and the second parity codes. An associated memory device and the controller thereof are further provided.

Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. An associated memory device and the controller thereof are further provided.

Abstract: Configurable permutators in an LDPC decoder are provided. A partially-parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multi-mode function. To overcome the difficulty in efficient implementation of a high-throughput decoder, the variable nodes are partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and, hence, increase the maximum operating frequency. In addition, shuffled message-passing decoding can be adopted in decoders according to the invention to increase the convergence speed, which reduces the number of iterations required to achieve a given bit-error-rate performance.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device comprises a memory and a controller. The memory is for data storage. When the data storage device receives first source data to be written to the memory from a host, the controller generates at least one first input data according to the first source data, scrambles the first input data according to a plurality of pseudo random sequences to obtain a plurality of first scrambled signals, calculates a plurality of transmission powers of the first scrambled signals, and selects a target scrambled signal with a lowest transmission power to be stored in the memory from the first scrambled signals.

Abstract: The invention provides a data read method. First, a training sequence stored in a storage unit of a memory is read according to at least one sense voltage to obtain a read-out training sequence. Whether the read-out training sequence is correct is then determined. When the read-out training sequence is not correct, the sense voltage is adjusted.

Abstract: A method for preventing a data storage device from data shift errors is provided. First, data is encoded into an error correction code. The error correction code is then scrambled to obtain a scrambled code to be stored in a memory. The scrambled code is then retrieved from the memory to obtain first read-out data. The first read-out data is then descrambled to obtain a first descrambled error correction code. The first descrambled error correction code is then decoded to determine whether the first descrambled error correction code has uncorrectable errors. When the first descrambled error correction code has uncorrectable errors, the scrambled code stored in the memory is read again to output second read-out data without shift errors. Following, the second read-out data is then descrambled to obtain a second descrambled error correction code, and the second descrambled error correction code is then decoded to recover the data.

Abstract: The invention provides a method for encoding and decoding an error correction code. First, raw data is received and then divided into a plurality of data segments. A plurality of short parities corresponding to the data segments is then generated according to a first generator polynomial. The short parities are then appended to the data segments to obtain a plurality of short codewords. The short codewords are then concatenated to obtain a code data. A long parity corresponding to the code data is then generated according to a second generator polynomial, wherein the first generator polynomial is a function of at least one minimum polynomial of the second generator polynomial. Finally, the long parity is then appended to the code data to obtain a long codeword as an error correction code corresponding to the raw data.

Abstract: The invention provides a controller. In one embodiment, the controller is coupled to a flash memory and a host, and comprises a selective mapper and an error correction code encoder. The selective mapper receives first source data, processes the first source data according to a plurality of pseudo random sequences to obtain a plurality of first mapped data segments, calculates a plurality of cross correlation values between prior data and the first mapped data segments, selects an optimal mapped data segment from the first mapped data segments according to the cross correlation values, and generates output mapped data according to the optimal mapped data segment. The error correction code encoder encodes a first error correction code to be stored in the flash memory according to the output mapped data.

Abstract: The invention provides a method for decoding an error correction code. First, an error syndrome of the error correction code is calculated. A plurality of coefficients of an error locator polynomial of the error correction code is then sequentially determined according to the error syndrome. When a new coefficient of the error locator polynomial is determined, it is also determined whether the new determined coefficient is equal to zero. When the new determined coefficient is equal to zero, a speculated error locator polynomial is built according to a plurality of low-order-term coefficients of the error locator polynomial, wherein the orders of the low-order-term coefficients are lower than that of the new determined coefficient. A Chien search is then performed to determine a plurality of roots of the speculated error locator polynomial. The error correction code is then corrected according to the roots of the speculated error locator polynomial.

Abstract: A decoding method for quasi-cyclic low-density parity-check (QC-LDPC) codes sequentially decodes a plurality of block codes defined by an identical parity-check matrix derived from a parity-check matrix of the QC-LDPC codes, wherein size of the identical parity-check matrix is smaller than size of the parity-check matrix.

Abstract: A welding flux for use in welding stainless steel parts to increase welding penetration, consisting essentially a base material obtained from manganese peroxide (MnO2), and an activator selected from a material group that includes zinc oxide (ZnO), silicon dioxide (SiO2), chromium oxide (CrO2), titanium dioxide (TiO2), molybdenum dioxide (MoO2), and iron oxide (Fe2O2).

Abstract: A welding flux for use in welding stainless steel parts to increase welding penetration, consisting essentially a base material obtained from manganese peroxide (MnO2), and an activator selected from a material group that includes zinc oxide (ZnO), silicon dioxide (SiO2), chromium oxide (CrO2), titanium dioxide (TiO2), molybdenum dioxide (MoO2), and iron oxide (Fe2O2).