Patents by Inventor Tsung-Ching HUANG

Tsung-Ching HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10855280
    Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Publication number: 20200335595
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first metal gate structure in a first dielectric layer. The method includes forming a second metal gate structure in the first dielectric layer, and the second metal gate structure includes a second metal electrode over a second gate dielectric layer. The method also includes forming a mask structure covering the first metal gate structure. The method includes etching a portion of the second gate dielectric layer and a portion of the second metal electrode of the second metal gate structure to form a first conductive portion extending above a top surface of the second gate dielectric layer. The method includes forming a metal layer over the first conductive portion, and the metal layer has a recess, and a top portion of the first conductive portion extends into the recess.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Ching HUANG, Tsung-Yu CHIANG
  • Patent number: 10805004
    Abstract: Examples described herein relate to reducing a magnitude of a supply voltage for a circuit element of an optical transmitter device. In some such examples, the circuit element is a driving element that is to receive a first electrical data signal and to provide a second electrical data signal to an optical element that is to provide an optical data signal. A testing element is to compare the optical data signal to the first electrical data signal to determine whether the optical transmitter device meets a performance threshold. When the device meets the performance threshold, a regulating element is to reduce a magnitude of the supply voltage of the driving element.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 13, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Tsung Ching Huang, Rui Wu, Nan Qi, Mir Ashkan Seyedi, Marco Fiorentino, Raymond G. Beausoleil
  • Publication number: 20200287528
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Publication number: 20200272037
    Abstract: A light source heat-dissipating device is disposed in a projection apparatus having a casing with an air inlet. The light source heat-dissipating device has a heat-dissipating fin assembly disposed in the casing and having an air intake side, and first and second heat-dissipating fin assemblies, a first air duct, and a fan adjacent to the first and second heat-dissipating fin assemblies. The second heat-dissipating fin assembly is stacked on the first one. The first heat-dissipating fin assembly is between the second one and the air inlet. The first air duct is adjacently-disposed at the air intake side, has a first entrance end connected with the air inlet and a first exit end opposite to the first entrance. The light source heat-dissipating device and projection apparatus improve temperature and life consistency between light source modules. The heat dissipation performances of the first and second heat-dissipating fin assemblies tend to be consistent.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 27, 2020
    Inventors: CHUN-LUNG YEN, TE-TANG CHEN, WEN-JUI HUANG, TSUNG-CHING LIN
  • Publication number: 20200274535
    Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Patent number: 10707316
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a dielectric layer over the substrate, a first metal gate structure in the dielectric layer and having a first width and a second metal gate structure in the dielectric layer and having a second width. The first metal gate structure includes a first metal electrode, and the second metal gate structure includes a second metal electrode. The second metal electrode includes a first conductive portion having a third width and a second conductive portion over the first conductive portion and having a fourth width. The fourth width is greater than the third width. The semiconductor device structure also includes two first source/drain portions at opposite sides of the first metal gate structure, and two second source/drain portions at opposite sides of the second metal gate structure.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ching Huang, Tsung-Yu Chiang
  • Patent number: 10686434
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 10673437
    Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Publication number: 20200152599
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventors: ALEXANDER KALNITSKY, YI-YANG LEI, HSI-CHING WANG, CHENG-YU KUO, TSUNG LUNG HUANG, CHING-HUA HSIEH, CHUNG-SHI LIU, CHEN-HUA YU, CHIN-YU KU, DE-DUI LIAO, KUO-CHIO LIU, KAI-DI WU, KUO-PIN CHANG, SHENG-PIN YANG, ISAAC HUANG
  • Patent number: 10651296
    Abstract: Methods of fabricating FinFET devices are provided. The method includes forming a fin over a substrate. The method also includes implanting a first dopant on a top surface of the fin and implanting a second dopant on a sidewall surface of the fin. The first dopant is different from the second dopant. The method further includes forming an oxide layer on the top surface and the sidewall surface of the fin, and forming a gate electrode layer over the oxide layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Han Wu, Tong-Min Weng, Chun-Yi Huang, Po-Ching Lee, Chih-Hsuan Hsieh, Shu-Ching Tsai
  • Publication number: 20200145100
    Abstract: Examples described herein relate to reducing a magnitude of a supply voltage for a circuit element of an optical transmitter device. In some such examples, the circuit element is a driving element that is to receive a first electrical data signal and to provide a second electrical data signal to an optical element that is to provide an optical data signal. A testing element is to compare the optical data signal to the first electrical data signal to determine whether the optical transmitter device meets a performance threshold. When the device meets the performance threshold, a regulating element is to reduce a magnitude of the supply voltage of the driving element.
    Type: Application
    Filed: April 7, 2017
    Publication date: May 7, 2020
    Inventors: Tsung Ching Huang, Rui Wu, Nan Qi, Mir Ashkan Seyedi, Marco Fiorentino
  • Patent number: 10637500
    Abstract: An acceleration apparatus applied in an artificial neuron is disclosed. The acceleration apparatus comprises an AND gate array, a first storage device, a second storage device and a multiply-accumulate (MAC) circuit. The AND gate array with plural AND gates receives a first bitmap and a second bitmap to generate an output bitmap. The first storage device stores a first payload and outputs a corresponding non-zero first element according to a first access address associated with a result of comparing the first bitmap with the output bitmap. The second storage device stores a second payload and outputs a corresponding non-zero second element according to a second access address associated with a result of comparing the second bitmap with the output bitmap. The MAC circuit calculates a dot product of two element sequences from the first storage device and the second storage device.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: April 28, 2020
    Assignee: BRITISH CAYMAN ISLANDS INTELLIGO TECHNOLOGY INC.
    Inventors: Chi-Hao Chen, Hong-Ching Chen, Chun-Ming Huang, Tsung-Liang Chen
  • Patent number: 10614945
    Abstract: A choke includes a single-piece core entirely made of a same material, the single-piece core having two boards and a pillar located between the two boards, a winding space being located among the two boards and the pillar, wherein the pillar has a non-circular and non-rectangular cross section along a direction substantially perpendicular to an axial direction of the pillar, the cross section of the pillar has a first axis and a second axis intersecting with each other at a center of the cross section of the pillar and are substantially perpendicular with each other, the first axis is longer than the second axis, and the cross section of the pillar is substantially symmetrical to both of the first axis and the second axis.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 7, 2020
    Assignee: CYNTEC CO., LTD.
    Inventors: Tsung-Chan Wu, Roger Hsieh, Yi-Min Huang, Lan-Chin Hsieh, Yu-Ching Kuo
  • Patent number: 10615878
    Abstract: An example system includes an optical modulator and a multiplexing controller. The modulator includes a data bus for receiving at least one data signal, a plurality of multiplexers and a plurality of modulating segments. Each multiplexer is coupled to the data bus to receive at least one data signal and to output a multiplexed signal. Each modulating segment may receive the multiplexed signal from one of the plurality of multiplexers and modulate the multiplexed signal using an optical input. The multiplexing controller may be in communication with the plurality of multiplexers and may configure each of the plurality of multiplexers in accordance with a selected modulation type.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: April 7, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Tsung-Ching Huang, Ashkan Seyedi, Chin-Hui Chen, Cheng Li, Marco Fiorentino, Raymond G. Beausoleil
  • Publication number: 20200035815
    Abstract: Methods of fabricating FinFET devices are provided. The method includes forming a fin over a substrate. The method also includes implanting a first dopant on a top surface of the fin and implanting a second dopant on a sidewall surface of the fin. The first dopant is different from the second dopant. The method further includes forming an oxide layer on the top surface and the sidewall surface of the fin, and forming a gate electrode layer over the oxide layer.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Han WU, Tong-Min WENG, Chun-Yi HUANG, Po-Ching LEE, Chih-Hsuan HSIEH, Shu-Ching TSAI
  • Patent number: 10546528
    Abstract: A current value of a first pixel and/or a current value of a second pixel of a display are adjusted until a value of a current difference is within a predetermined range. The current value of the first pixel corresponds to a brightness level of the first pixel. The current value of the second pixel corresponds to a brightness level of the second pixel. Adjusting the current value of the first pixel involves adjusting a threshold voltage value of a transistor of the first pixel. Adjusting the current value of the second pixel involves adjusting a threshold voltage value of a transistor of the second pixel.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: January 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching Huang, Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin
  • Publication number: 20200027750
    Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
  • Patent number: 10535629
    Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
  • Patent number: 10503851
    Abstract: In example implementations, a method executed by a processor is provided. The method receives a simulated photonic data input based on a theoretical photonic design that meets a target specification. A complementary metal-oxide semiconductor (CMOS) circuit design is designed based on the simulated photonic data input using a pre-layout simulation. An experimental photonic data input based on a fabricated photonics device that meets the target specification is received. The CMOS circuit is designed based on the experimental photonic data input using a post-layout simulation. A physical circuit CMOS circuit design and a layout that includes detailed physical dimensions associated with the physical CMOS circuit design that is based on the pre-layout and the post-layout are transmitted to a CMOS foundry.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: December 10, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Tsung-Ching Huang, Chin-Hui Chen, Marco Fiorentino, Raymond G. Beausoleil