Patents by Inventor Tsung-Ching HUANG
Tsung-Ching HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150145579Abstract: A circuit includes a first circuit, a second circuit and a third circuit. The first circuit is configured to receive a first phase of a clock signal, a second phase of a clock signal and a first control signal. The first circuit is configured to generate a first interpolated phase of a clock signal. The second circuit is configured to receive a third phase of a clock signal, a fourth phase of a clock signal and a second control signal, and generate a second interpolated phase of a clock signal. The third circuit is configured to receive the first interpolated phase of the clock signal and the second interpolated phase of the clock signal, and generate the first control signal. The first control signal dynamically adjusts the first interpolated phase of the clock signal.Type: ApplicationFiled: November 25, 2013Publication date: May 28, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTUING COMPANY, LTD.Inventors: Chih-Chang LIN, Chan-Hong CHERN, Tsung-Ching HUANG, Ming-Chieh HUANG
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Publication number: 20150145597Abstract: A multi-stage transimpedance amplifier (TIA) which includes a common gate amplifier configured to receive a current signal, the common gate amplifier is configured to convert the current signal into an amplified voltage signal. The multi-stage TIA further includes a capacitive degeneration amplifier configured to receive the amplified voltage signal, the capacitive degeneration amplifier is configured to equalize the amplified voltage signal to form an equalized signal. The multi-stage TIA further includes an inverter configured to receive the equalized signal, the inverter is configured to increase a signal strength of the equalized signal to form an output signal. The multi-stage TIA further includes a feedback configured to receive the output signal, wherein the feedback is connected to an input and an output of the inverter.Type: ApplicationFiled: November 25, 2013Publication date: May 28, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Ching HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN
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Publication number: 20150014518Abstract: A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to receive an input signal. A second inverter has a second input node and a second output node. The second input node connects to a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node. A first amplifier is configured to provide feedback to the first input node and a second amplifier is configured to provide feedback to the second input node.Type: ApplicationFiled: October 1, 2014Publication date: January 15, 2015Inventors: Tsung-Ching HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Ming-Chieh HUANG, Chih-Chang LIN
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Patent number: 8903030Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.Type: GrantFiled: November 7, 2012Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei, Tsung-Ching Huang
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Publication number: 20140347110Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.Type: ApplicationFiled: August 11, 2014Publication date: November 27, 2014Inventors: Chan-Hong CHERN, Tao Wen CHUNG, Ming-Chieh HUANG, Chih-Chang LIN, Tsung-Ching HUANG, Fu-Lung HSUEH
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Patent number: 8878585Abstract: A slicer includes a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal. The first latch further includes a developing transistor configured to receive a second clock signal, wherein the first clock signal is different from the second clock signal. The first latch further includes a first input transistor configured to receive a first input. The first latch further includes a second input transistor configured to receive a second input, wherein the first and second input transistors are connected with the developing transistor. The first latch further includes at least one pre-charging transistor configured to receive a third clock signal, wherein the at least one pre-charging transistor is connected to a first output node and a second output node. The slicer further includes a second latch connected to the first and second output nodes and to a third output node.Type: GrantFiled: January 8, 2014Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Tsung-Ching Huang, Derek C. Tao
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Patent number: 8872592Abstract: A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.Type: GrantFiled: June 19, 2012Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ching Huang, Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin
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Patent number: 8862951Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.Type: GrantFiled: June 21, 2012Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tao Wen Chung, Yuwen Swei, Chih-Chang Lin, Tsung-Ching Huang
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Patent number: 8847652Abstract: The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.Type: GrantFiled: July 26, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Ming-Chieh Huang, Tsung-Ching Huang, Fu-Lung Hsueh
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Patent number: 8816732Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.Type: GrantFiled: June 22, 2012Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching Huang, Fu-Lung Hsueh
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Publication number: 20140126656Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tao Wen CHUNG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Yuwen SWEI, Tsung-Ching HUANG
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Publication number: 20140119426Abstract: A slicer includes a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal. The first latch further includes a developing transistor configured to receive a second clock signal, wherein the first clock signal is different from the second clock signal. The first latch further includes a first input transistor configured to receive a first input. The first latch further includes a second input transistor configured to receive a second input, wherein the first and second input transistors are connected with the developing transistor. The first latch further includes at least one pre-charging transistor configured to receive a third clock signal, wherein the at least one pre-charging transistor is connected to a first output node and a second output node. The slicer further includes a second latch connected to the first and second output nodes and to a third output node.Type: ApplicationFiled: January 8, 2014Publication date: May 1, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Chih-Chang LIN, Tsung-Ching HUANG, Derek C. TAO
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Patent number: 8643422Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.Type: GrantFiled: July 12, 2012Date of Patent: February 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Tsung-Ching Huang, Derek C. Tao
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Publication number: 20140028407Abstract: The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.Type: ApplicationFiled: July 26, 2012Publication date: January 30, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Ming-Chieh Huang, Tsung-Ching Huang, Fu-Lung Hsueh
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Publication number: 20140015582Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.Type: ApplicationFiled: July 12, 2012Publication date: January 16, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Chih-Chang LIN, Tsung-Ching HUANG, Derek C. TAO
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Publication number: 20140002332Abstract: A current value of a first pixel and/or a current value of a second pixel of a display are adjusted until a value of a current difference is acceptable. The current value of the first pixel corresponds to a brightness level of the first pixel. The current value of the second pixel corresponds to a brightness level of the second pixel. Adjusting the current value of the first pixel involves adjusting a threshold voltage value of a transistor of the first pixel. Adjusting the current value of the second pixel involves adjusting a threshold voltage value of a transistor of the second pixel.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Ching HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Ming-Chieh HUANG, Chih-Chang LIN
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Publication number: 20130346811Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.Type: ApplicationFiled: June 21, 2012Publication date: December 26, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Yuwen SWEI, Chih-Chang LIN, Tsung-Ching HUANG
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Publication number: 20130342247Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chan-Hong CHERN, Tao Wen CHUNG, Ming-Chieh HUANG, Chih-Chang LIN, Tsung-Ching HUANG, Fu-Lung HSUEH
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Publication number: 20130335145Abstract: A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.Type: ApplicationFiled: June 19, 2012Publication date: December 19, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Ching HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Ming-Chieh HUANG, Chih-Chang LIN