Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.

Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.

Abstract: A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.

Abstract: An example system includes an optical modulator and a multiplexing controller. The modulator includes a data bus for receiving at least one data signal, a plurality of multiplexers and a plurality of modulating segments. Each multiplexer is coupled to the data bus to receive at least one data signal and to output a multiplexed signal. Each modulating segment may receive the multiplexed signal from one of the plurality of multiplexers and modulate the multiplexed signal using an optical input. The multiplexing controller may be in communication with the plurality of multiplexers and may configure each of the plurality of multiplexers in accordance with a selected modulation type.

Abstract: In example implementations, a method executed by a processor is provided. The method receives a simulated photonic data input based on a theoretical photonic design that meets a target specification. A complementary metal-oxide semiconductor (CMOS) circuit design is designed based on the simulated photonic data input using a pre-layout simulation. An experimental photonic data input based on a fabricated photonics device that meets the target specification is received. The CMOS circuit is designed based on the experimental photonic data input using a post-layout simulation. A physical circuit CMOS circuit design and a layout that includes detailed physical dimensions associated with the physical CMOS circuit design that is based on the pre-layout and the post-layout are transmitted to a CMOS foundry.

Abstract: A circuit includes an output node, a set of first transistors, a set of second transistors, and a first and second power node. The first power node is configured to carry a first voltage level, and second power node is configured to carry a second voltage level. Set of first transistors is coupled between the first power node and output node. Set of second transistors is coupled between the second power node and output node. The first control signal generating circuit is coupled to a gate of a first transistor of the set of first transistors and a gate of a first transistor of the set of second transistors. The first control signal generating circuit is configured to generate a set of biasing signals for the gate of the first transistor of the set of first transistors and the gate of the first transistor of the set of second transistors.

Abstract: In the examples provided herein, a vascular pattern recognition system integrated onto a portable card includes a vascular pattern detection system to obtain image data of blood vessels of a finger to be swiped across a detection area on the portable card, wherein the vascular pattern detection system includes a near infrared light source and an image sensor array. The vascular pattern recognition system also includes an image processor to process the image data to generate a scanned vascular pattern and compare the scanned vascular pattern to a pre-stored pattern stored on the portable card to authenticate the image data, and a security processor to generate a transaction code to authorize a transaction upon authentication of the image data.

Abstract: In one example, a device to process analog sensor data is described. For example, a device may include at least one analog sensor to generate a first set of analog voltage signals and a crossbar array including a plurality of memristors. In one example, the crossbar array is to receive an input vector of the first set of analog voltage signals, generate an output vector comprising a second set of analog voltage signals that is based upon a dot product of the input vector and a matrix comprising resistance values of the plurality of memristors, detect a pattern of the output vector, and activate a processor upon a detection of the pattern.

Abstract: In the examples provided herein, a vascular pattern recognition system integrated onto a portable card includes a vascular pattern detection system to obtain image data of blood vessels of a finger to be swiped across a detection area on the portable card, wherein the vascular pattern detection system includes a near infrared light source and an image sensor array. The vascular pattern recognition system also includes an image processor to process the image data to generate a scanned vascular pattern and compare the scanned vascular pattern to a pre-stored pattern stored on the portable card to authenticate the image data, and a security processor to generate a transaction code to authorize a transaction upon authentication of the image data.

Abstract: A circuit includes a startup circuit to provide a charging signal to initiate startup of a reference circuit. The startup circuit includes a detector circuit having a detector current path control, a level shifter having a level shifter current path control, and a charger circuit having a charger current path control. Each of the detector current path control, the level shifter current path control, and the charger circuit current path control enable current flow in the startup circuit when the charger turn-on signal is in the on-state and disable the current flow in the startup circuit when the charger turn-on signal is in the off state.

Abstract: Examples described herein relate to a driver circuit. In an example, the circuit includes a first input for receiving a first signal and a second input for receiving a second signal that is an inverse of the first signal. The circuit also includes a first driver array electrically coupling the first input to a first DC isolator and a first delay tap line electrically coupling the second input to the first DC isolator. The circuit further includes a second driver array electrically coupling the second input to a second DC isolator and a second delay tap line electrically coupling the first input to the second DC isolator. A carrier controller of the circuit is electrically coupled between the first DC isolator and the second DC isolator.

Abstract: A circuit includes a first circuit, a second circuit and a third circuit. The first circuit is configured to receive a first phase of a clock signal, a second phase of a clock signal and a first control signal. The first circuit is configured to generate a first interpolated phase of a clock signal. The second circuit is configured to receive a third phase of a clock signal, a fourth phase of a clock signal and a second control signal, and generate a second interpolated phase of a clock signal. The third circuit is configured to receive the first interpolated phase of the clock signal and the second interpolated phase of the clock signal, and generate the first control signal. The first control signal dynamically adjusts the first interpolated phase of the clock signal.

Abstract: Examples described herein relate to a driver circuit. In an example, the circuit includes a first input for receiving a first signal and a second input for receiving a second signal that is an inverse of the first signal. The circuit also includes a first driver array electrically coupling the first input to a first DC isolator and a first delay tap line electrically coupling the second input to the first DC isolator. The circuit further includes a second driver array electrically coupling the second input to a second DC isolator and a second delay tap line electrically coupling the first input to the second DC isolator. A carrier controller of the circuit is electrically coupled between the first DC isolator and the second DC isolator.

Abstract: In the examples provided herein, a vascular pattern recognition system integrated onto a portable card includes a vascular pattern detection system to obtain image data of blood vessels of a finger to be swiped across a detection area on the portable card, wherein the vascular pattern detection system includes a near infrared light source and an image sensor array. The vascular pattern recognition system also includes an image processor to process the image data to generate a scanned vascular pattern and compare the scanned vascular pattern to a pre-stored pattern stored on the portable card to authenticate the image data, and a security processor to generate a transaction code to authorize a transaction upon authentication of the image data.

Abstract: A voltage supply unit includes a regulator unit, a current mirror, and a cascode unit. The regulator unit is configured to receive first and second voltage signals and generate a third voltage signal. The current mirror is configured to generate first and second current signals based on the third voltage signal. The cascode unit includes a first terminal configured to receive the first current signal, a second terminal configured to receive a first bias voltage signal, a third terminal configured to receive a second bias voltage signal, and a fourth terminal electrically connected to the regulator unit. An output voltage supply signal is controlled by the second current signal.

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract: A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller.

Abstract: A circuit includes an output node, a set of first transistors, a set of second transistors, and a first and second power node. The first power node is configured to carry a first voltage level, and second power node is configured to carry a second voltage level. Set of first transistors is coupled between the first power node and output node. Set of second transistors is coupled between the second power node and output node. The first control signal generating circuit is coupled to a gate of a first transistor of the set of first transistors and a gate of a first transistor of the set of second transistors. The first control signal generating circuit is configured to generate a set of biasing signals for the gate of the first transistor of the set of first transistors and the gate of the first transistor of the set of second transistors.

Abstract: An initialization device for a charge pump includes a driving circuit and a bias voltage circuit. The driving circuit is between two power supply nodes. The driving circuit includes a first node configured to be coupled to an output electrode of a capacitor in the charge pump. The bias voltage circuit is coupled to the two power supply nodes. The bias voltage circuit includes a second node coupled to a control terminal of the driving circuit. In response to an applied initialization signal, the bias voltage circuit is configured to output a bias voltage to the second node. The bias voltage has at least two levels that correspond to levels of the applied initialization signal. In response to the bias voltage, the driving circuit is configured to output an output signal having at least two levels that correspond to the at least two levels of the bias voltage.

Abstract: A circuit includes a first power node, a second power node, an output node, a plurality of first transistors and a plurality of second transistors. The plurality of first transistors is serially coupled between the first power node and the output node. The plurality of second transistors is serially coupled between the second power node and the output node.