Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Abstract: A method of forming a semiconductor device package includes bonding a first connector to a first conductive structure on a first package. The method includes bonding a die to a surface of the first package, wherein a top surface of the first connector extends above a top surface of the die. The method includes surrounding the first connector with a molding compound. The method includes removing a portion of the first connector and a portion of the molding compound. The top surface of the remaining first conductor is below the top surface of the die. A first top surface of the remaining molding compound is below the top surface of the die. A second top surface of the remaining molding compound is level with the top surface of the die. The method includes bonding a second connector to the remaining portion of the first connector.

Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.

Abstract: A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package.

Abstract: A device comprises a substrate having a die mounted on the first side of the substrate and a moldable underfill (MUF) disposed on the first side of the substrate and around the die. An interposer is mounted on the first side of the substrate, with the interposer having lands disposed on a first side of the interposer. The interposer mounted to the substrate by connectors bonded to a second side of the interposer, the connectors providing electrical connectivity between the interposer and the substrate. A package is mounted on the first side of the interposer and is electrically connected to the lands. At least one of the lands is aligned directly over the die and wherein a pitch of the connectors is different than a pitch of the lands.

Abstract: A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die.

Abstract: A package includes a printed circuit board (PCB), and a die bonded to the PCB through solder balls. A re-workable underfill is dispensed in a region between the PCB and the die.

Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region. The scribe line region is positioned between the first chip region and the second chip region. The method also includes forming a bump over the passivation layer on at least one of the first chip region and the second chip region. The method further includes removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region. The method additionally includes filling the groove with a molding compound layer. The molding compound layer is filled to a point that entirely fills the groove, covers the passivation layer, and covers a lower portion of the bump. The method also includes separating the first chip region from the second chip region along the scribe line region.

Abstract: A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

Abstract: Integrated circuit (IC) packages and methods of forming the IC packages are provided. In an embodiment, IC dies are formed and are placed on a carrier to form a packaged semiconductor device. An encapsulant is formed over the IC dies and between the neighboring IC dies. The encapsulant and the IC dies are planarized to expose contacts on top surfaces of the IC dies, and redistribution layers (RDLs) are formed over the planarized encapsulant and the planarized IC dies. Openings are formed in a topmost dielectric layer of the RDLs to expose interconnects in the RDL, and a conductive seed layer is formed over the RDL and in the openings. Connectors of a first type and connectors of a second type are formed over the seed layer in the openings. The packaged semiconductor device is diced into individual IC packages.

Abstract: Stacked semiconductor devices and methods of forming the same are disclosed. First tier workpieces are mounted on a top surface of a semiconductor device to form first tier stacks, the semiconductor device comprising one or more integrated circuit dies, the semiconductor device having one or more test pads per integrated circuit die on the top surface of the semiconductor device. Each of the first tier stacks is electrically tested to identify first known good stacks and first known bad stacks. Second tier workpieces are mounted atop the first known good stacks, thereby forming second tier stacks. Each of the second tier stacks is electrically tested to identify second known good stacks and second known bad stacks. Stacking process further comprises one or more workpiece mounting/testing cycles. The stacking process continues until the stacked semiconductor devices comprise desired number of workpieces.

Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.

Abstract: A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package.

Abstract: A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package.

Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess.

Abstract: In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.

Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.