Abstract: A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to the substrate. The semiconductor die comprises a bump and a molding compound layer in physical contact with a lower portion of the bump. An upper portion of the bump is in physical contact with the no-flow underfill layer.

Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.

Abstract: An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole.

Abstract: An embodiment device includes a first die, a first molding compound extending along sidewalls of the first die, and one or more first redistribution layers (RDLs) on the first die and the first molding compound. The device further includes a device package comprising a plurality of second dies, wherein the device package is bonded to an opposing surface of the one or more first RDLs as the first die and the first molding compound. A package substrate is bonded to the opposing surface of the one or more first RDLs. The package substrate is electrically connected to the first die and the plurality of second dies.

Abstract: An embodiment device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs extend laterally past edges of the first die. The device package further includes one or more second dies bonded to a first surface of the one or more RDLs and a connector element on the first surface of the one or more RDLs. The connector element has a vertical dimension greater than the one or more second dies. A package substrate is bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate.

Abstract: An embodiment device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

Abstract: An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Abstract: A method of forming a semiconductor device package includes bonding a first connector to a first conductive structure on a first package. The method includes bonding a die to a surface of the first package, wherein a top surface of the first connector extends above a top surface of the die. The method includes surrounding the first connector with a molding compound. The method includes removing a portion of the first connector and a portion of the molding compound. The top surface of the remaining first conductor is below the top surface of the die. A first top surface of the remaining molding compound is below the top surface of the die. A second top surface of the remaining molding compound is level with the top surface of the die. The method includes bonding a second connector to the remaining portion of the first connector.

Abstract: A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.

Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer.

Abstract: A package assembly including a semiconductor die electrically coupled to a substrate by an interconnected joint structure. The semiconductor die includes a bump overlying a semiconductor substrate, and a molding compound layer overlying the semiconductor substrate and being in physical contact with a first portion of the bump. The substrate includes a no-flow underfill layer on a conductive region. A second portion of the bump is in physical contact with the no-flow underfill layer to form the interconnected joint structure.

Abstract: A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die. The method further includes bonding the second connector to a remaining portion of the first connector.

Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer.

Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a pillar bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die.

Abstract: An integrated circuit structure includes a first die including TSVs; a second die over and bonded to the first die, with the first die having a surface facing the second die; and a molding compound including a portion over the first die and the second die. The molding compound contacts the surface of the second die. Further, the molding compound includes a portion extending below the surface of the second die.

Abstract: A device includes a first package component and the second package component. The first package component includes a first plurality of connectors at a top surface of the first package component, and a second plurality of connectors at the top surface. The second package component is over and bonded to the first plurality of connectors, wherein the second plurality of connectors is not bonded to the second package component. A solder resist is on the top surface of the first package component. A trench is disposed in the solder resist, wherein a portion of the trench spaces the second plurality of connectors apart from the first plurality of connectors.

Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.

Abstract: A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die. The method further includes bonding the second connector to a remaining portion of the first connector.