Abstract: An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

Abstract: An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.

Abstract: An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

Abstract: An integrated circuit structure includes an integrated circuit structure includes a substrate, insulation regions over the substrate, and a fin field-effect transistor (FinFET). The FinFET includes a plurality of fins over the substrate, wherein each of the plurality of fins comprises a first fin portion and a second fin portion, a gate stack on a top surface and sidewalls of the first fin portion of each of the plurality of fins, an epitaxial semiconductor layer comprising a portion directly over the second fin portion of each of the plurality of fins, and sidewall portions directly over the insulation regions, and a silicide layer on, and having an interface with, the epitaxial layer, wherein a peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of peripherals of the plurality of fins is greater than 1.

Abstract: In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of the respective active area. The edges of the at least three active areas form an arc.

Abstract: A field effect transistor including a substrate which includes, a fin structure, the fin structure having a top surface. The field effect transistor further including an isolation in the substrate and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the fin structure and the isolation structure. The S/D recess cavity includes a lower portion, the lower portion further includes a first strained layer, a first dielectric film and a second dielectric film, wherein the first strained layer is disposed between the first dielectric film and the second dielectric film. The S/D recess cavity further includes an upper portion including a second strained layer overlying the first strained layer, wherein a ratio of a height of the upper portion to a height of the lower portion ranges from about 0.8 to about 1.2.

Abstract: A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.

Abstract: A method of fabricating a semiconductor device includes providing a substrate having a fin disposed thereon. A gate structure is formed on the fin. The gate structure interfaces at least two sides of the fin. A stress film is formed on the substrate including on the fin. The substrate including the stress film is annealed. The annealing provides a tensile strain in a channel region of the fin. For example, a compressive strain in the stress film may be transferred to form a tensile stress in the channel region of the fin.

Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.

Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.

Abstract: An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

Abstract: An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.

Abstract: A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.

Abstract: A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate and a 3D structure disposed over the substrate. The semiconductor device further includes a dielectric layer disposed over the 3D structure, a WFMG layer disposed over the dielectric layer, and a gate structure disposed over the WFMG layer. The gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure. The source and drain region define a channel region therebetween. The gate structure induces a stress in the channel region.

Abstract: In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.

Abstract: The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening having a second width W2 less than the first width. The patterned mask layer defines a multi-fin device region and an inter-device region, wherein the inter-device region is aligned with the first opening; and the multi-fin device region includes at least one intra-device region being aligned with the second opening.

Abstract: The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.