Abstract: A surveillance method, a surveillance apparatus, and a marking module are applied to an active burglarproof system. The surveillance method includes the following steps. Determine whether a first wireless signal related to a marking module is received in a first sensing region, to produce a first determination result. Determine whether the first wireless signal is received in a second sensing region, to produce a second determination result. Selectively generate a warning signal according to the first determination result and the second determination result.

Abstract: FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer.

Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Abstract: A semiconductor device includes a substrate having a first region and a second region, an n-type transistor in the first region, the n-type transistor comprising a first set of source/drain features, and a p-type transistor in the second region, the p-type transistor comprising a second set of source/drain features. The second set of source/drain features extend deeper than the first set of source/drain features.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.

Abstract: An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.

Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.

Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.

Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.

Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.

Abstract: A semiconductor device includes a substrate having a first region and a second region, an n-type transistor in the first region, the n-type transistor comprising a first set of source/drain features, and a p-type transistor in the second region, the p-type transistor comprising a second set of source/drain features. The second set of source/drain features extend deeper than the first set of source/drain features.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features, after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features, forming a semiconductor layer over the anti-punch-through features, and forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features

Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing an annealing process to change a composition of a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.

Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing a high-pressure-anneal process to a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.

Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing an annealing process to change a composition of a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.

Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first mask on a substrate; defining a first doped region through an opening of the first mask; forming a second mask on the first mask and filling in the opening of the first mask with the second mask; defining a second doped region through an opening of the second mask; and stripping the first mask and the second mask from the substrate. The present disclosure provides a semiconductor structure, including a substrate having a top surface; a first doped region having a first surface; and a second doped region having a second surface. The first surface and the second surface are coplanar with the top surface of the substrate. Either of the doped regions has a monotonically decreasing doping profile from the top surface of the substrate to a bottom of the doped region.