Patents by Inventor Tsung-Lin Lee
Tsung-Lin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9953885Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.Type: GrantFiled: July 26, 2010Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Yuan, Tsung-Lin Lee, Hung-Ming Chen, Chang-Yun Chang
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Patent number: 9887100Abstract: Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes fins. Gates are disposed over the fins, the gates being substantially perpendicular to the fins. A source/drain region is disposed on each of fins between two of the gates. A contact is coupled to the source/drain region between the two of the gates. The source/drain region comprises a first width, and the contact comprises a second width. The second width is substantially the same as the first width.Type: GrantFiled: October 3, 2014Date of Patent: February 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Tsung-Lin Lee, Wei-Jen Lai, Chih Chieh Yeh
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Patent number: 9847334Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate with a first lattice constant and having a PMOS region and an NMOS region. The semiconductor device further includes first and second fin structures over the PMOS region and NMOS region respectively. The first fin structure includes a buffer layer with a second lattice constant and a first channel layer. The lattice constant difference between the first channel layer and the buffer layer is smaller than that between the first channel layer and the semiconductor layer. The first channel layer has a third lattice constant, which is greater than the second lattice constant. The first lattice constant is greater than the second lattice constant. The second fin structure includes a second channel layer. The second channel layer has a fourth lattice constant which is less than the first lattice constant.Type: GrantFiled: November 18, 2016Date of Patent: December 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Zheng-Yang Pan, Tsung-Lin Lee, Shih-Chieh Chang
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Publication number: 20170358648Abstract: Various strained channel transistors are disclosed herein. An exemplary semiconductor device includes a substrate and a fin structure disposed over the substrate. The fin structure includes a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The second epitaxial layer includes a relaxed transversal stress component and a longitudinal compressive stress component, and the third epitaxial layer has uni-axial strain. A gate structure is disposed on a channel region of the fin structure, such that the gate structure interposes a source region and a drain region of the fin structure.Type: ApplicationFiled: August 25, 2017Publication date: December 14, 2017Inventors: MARK VAN DAL, GERBEN DOORNBOS, GEORGIOS VELLIANITIS, TSUNG-LIN LEE, FENG YUAN
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Patent number: 9761666Abstract: The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.Type: GrantFiled: June 16, 2011Date of Patent: September 12, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mark van Dal, Gerben Doornbos, Georgios Vellianitis, Tsung-Lin Lee, Feng Yuan
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Publication number: 20170243941Abstract: FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer.Type: ApplicationFiled: May 8, 2017Publication date: August 24, 2017Inventors: Chih Chieh Yeh, Cheng-Yi Peng, Tsung-Lin Lee
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Patent number: 9728461Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing a high-pressure-anneal process to a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.Type: GrantFiled: August 28, 2015Date of Patent: August 8, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yi Peng, Chia-Cheng Ho, Chih Chieh Yeh, Tsung-Lin Lee, Yu-Lin Yang
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Patent number: 9721829Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.Type: GrantFiled: January 22, 2016Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li Chiang, Wei-Jen Lai, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
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Patent number: 9711412Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.Type: GrantFiled: August 19, 2016Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Munufacturing Company, Ltd.Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
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Publication number: 20170148917Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: ApplicationFiled: February 6, 2017Publication date: May 25, 2017Inventors: TSUNG-LIN LEE, CHIH-HAO CHANG, CHIH-HSIN KO, FENG YUAN, JEFF J. XU
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Patent number: 9659826Abstract: A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features.Type: GrantFiled: December 5, 2016Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Jung-Piao Chiu, Tsung-Lin Lee, Chih Chieh Yeh, Chih-Sheng Chang, Yee-Chia Yeo
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Patent number: 9647071Abstract: FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer.Type: GrantFiled: June 15, 2015Date of Patent: May 9, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Tsung-Lin Lee
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Patent number: 9640441Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.Type: GrantFiled: July 1, 2016Date of Patent: May 2, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Ming Chen, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
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Publication number: 20170117388Abstract: An exemplary method of forming a fin field effect transistor that includes first and second etching processes to form a fin structure. The fin structure includes an upper portion and a lower portion separated at a transition. The upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.Type: ApplicationFiled: October 31, 2016Publication date: April 27, 2017Inventors: Feng YUAN, Hung-Ming CHEN, Tsung-Lin LEE, Chang-Yun CHANG, Clement Hsingjen WANN
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Publication number: 20170084498Abstract: A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features.Type: ApplicationFiled: December 5, 2016Publication date: March 23, 2017Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Jung-Piao Chiu, Tsung-Lin Lee, Chih Chieh Chang, Yee-Chia Yeo
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Patent number: 9601587Abstract: A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape.Type: GrantFiled: January 23, 2015Date of Patent: March 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sey-Ping Sun, Tsung-Lin Lee, Chin-Hsiang Lin, Chih-Hao Chang, Chen-Nan Yeh, Chao-An Jong
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Patent number: 9577071Abstract: A method of fabricating a field effect transistor (FET) includes forming a channel portion over a first surface of a substrate, wherein the channel portion comprises germanium and defines a second surface above the first surface. The method further includes forming cavities that extend through the channel portion and into the substrate. The method further includes epitaxially-growing a strained material in the cavities, wherein the strained material comprises SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn or a III-V material.Type: GrantFiled: October 6, 2015Date of Patent: February 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Cheng-Yi Peng, Clement Hsingjen Wann
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Patent number: 9564529Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: GrantFiled: September 3, 2015Date of Patent: February 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Patent number: 9558650Abstract: A surveillance method, a surveillance apparatus, and a marking module are applied to an active burglarproof system. The surveillance method includes the following steps. Determine whether a first wireless signal related to a marking module is received in a first sensing region, to produce a first determination result. Determine whether the first wireless signal is received in a second sensing region, to produce a second determination result. Selectively generate a warning signal according to the first determination result and the second determination result.Type: GrantFiled: April 9, 2015Date of Patent: January 31, 2017Assignee: AVER INFORMATION INC.Inventors: Yu-Chin Chou, Wei-Hsiao Wang, Hsin-Yen Lee, Jui-Hsuan Chiang, Tsung-Lin Lee, Chih-Hsin Tsao
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Publication number: 20160365414Abstract: FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer.Type: ApplicationFiled: June 15, 2015Publication date: December 15, 2016Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Tsung-Lin Lee