Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.

Abstract: A cell array structure includes a first resistive memory cell. The first resistive memory cell includes a well region, a first doped region, a merged region, a first gate structure, a second gate structure and a first metal layer. The first doped region is formed under a surface of the well region. The merged region is formed under the surface of the well region. The first gate structure is formed over the surface of the well region between the first doped region and the merged region. The first gate structure includes a first insulation layer and a first conductive layer. The second gate structure is formed over the merged region. The second gate structure includes a second insulation layer and a second conductive layer. The first metal layer is connected with the first doped region.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.

Abstract: A resistive random-access memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. The first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. A first metal layer is connected with the first doped region and the third doped region. A second metal layer is connected with the conductive layer of the first gate structure and the conductive layer of the third gate structure.

Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by performing computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Abstract: A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.

Abstract: A non-volatile memory cell includes a storage transistor having a first terminal, a second terminal, and a gate terminal. During a program operation, the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell, the second terminal of the storage transistor is floating, and the gate terminal of the storage transistor is coupled to a program voltage. The program voltage is greater than the data voltage.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.

Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by perform computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Abstract: A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.

Abstract: A random code generator includes a differential cell array, a power supply circuit, a first selecting circuit and a current judgment circuit. The power supply circuit receives an enrolling signal and a feedback signal. The first selecting circuit receives a first selecting signal. When the enrolling signal is activated and an enrollment is performed on the first differential cell, the power supply circuit provides an enrolling voltage, and the enrolling voltage is transmitted to a first storage element and a second storage element of the first differential cell through the first selecting circuit. Consequently, the cell current is generated. When a magnitude of the cell current is higher than a specified current value, the current judgment circuit activates the feedback signal, so that the power supply circuit stops providing the enrolling voltage.

Abstract: A non-volatile memory cell includes a storage transistor having a first terminal, a second terminal, and a gate terminal. During a program operation, the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell, the second terminal of the storage transistor is floating, and the gate terminal of the storage transistor is coupled to a program voltage. The program voltage is greater than the data voltage.

Abstract: A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.

Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.