Patents by Inventor Tsung-Mu Lai

Tsung-Mu Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9847133
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 19, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Shih-Chen Wang, Chen-Hao Po
  • Publication number: 20170206968
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Application
    Filed: November 16, 2016
    Publication date: July 20, 2017
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Publication number: 20170206970
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.
    Type: Application
    Filed: May 10, 2016
    Publication date: July 20, 2017
    Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Shih-Chen Wang, Chen-Hao Po
  • Patent number: 9524785
    Abstract: A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate transistor has a first terminal for receiving a bit line signal, a second terminal, and a floating gate. The word line transistor has a first terminal coupled to the second terminal of the floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal. A voltage passing device is for outputting a second voltage during an inhibit operation and a first voltage during a program operation or an erase operation. The first capacitance element is coupled to the first voltage passing device and the floating gate, and for receiving a first control signal. The second capacitance element is for receiving at a second control signal.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: December 20, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai
  • Publication number: 20160293261
    Abstract: A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate transistor has a first terminal for receiving a bit line signal, a second terminal, and a floating gate. The word line transistor has a first terminal coupled to the second terminal of the floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal. A voltage passing device is for outputting a second voltage during an inhibit operation and a first voltage during a program operation or an erase operation. The first capacitance element is coupled to the first voltage passing device and the floating gate, and for receiving a first control signal. The second capacitance element is for receiving at a second control signal.
    Type: Application
    Filed: March 10, 2016
    Publication date: October 6, 2016
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai
  • Patent number: 9041089
    Abstract: A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 26, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Wei-Ren Chen, Tsung-Mu Lai
  • Publication number: 20140361358
    Abstract: A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.
    Type: Application
    Filed: December 27, 2013
    Publication date: December 11, 2014
    Applicant: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Wei-Ren Chen, Tsung-Mu Lai
  • Patent number: 8278724
    Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: October 2, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hua Chang, Hua-Shu Wu, Tsung-Mu Lai
  • Patent number: 8089798
    Abstract: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: January 3, 2012
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho
  • Patent number: 7965481
    Abstract: A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: June 21, 2011
    Assignee: eMemory Technology Inc.
    Inventors: Shao-Chang Huang, Wei-Yao Lin, Tsung-Mu Lai
  • Patent number: 7872898
    Abstract: A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: January 18, 2011
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang, Tsung-Mu Lai
  • Publication number: 20100265755
    Abstract: A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 21, 2010
    Applicant: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang, Tsung-Mu Lai
  • Patent number: 7732299
    Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: June 8, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fa-Yuan Chang, Tsung-Mu Lai, Kai-Chih Liang, Hua-Shu Wu, Chin-Hsiang Ho, Gwo-Yuh Shiau, Chu-Wei Cheng, Ming-Chyi Liu, Yuan-Chih Hsieh, Chia-Shiung Tsai, Nick Y. M. Shen, Ching-Chung Pai
  • Patent number: 7728396
    Abstract: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 1, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hua-Shu Wu, Tsung-Mu Lai, Ming-Chih Chang, Che-Rong Laing
  • Publication number: 20100073985
    Abstract: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.
    Type: Application
    Filed: November 30, 2009
    Publication date: March 25, 2010
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho
  • Publication number: 20100006924
    Abstract: A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 14, 2010
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Hsin-Ming Chen, Shao-Chang Huang, Shih-Chen Wang, Tsung-Mu Lai, Ming-Chou Ho, Chrong-Jung Lin
  • Publication number: 20100002344
    Abstract: A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 7, 2010
    Inventors: Shao-Chang Huang, Wei-Yao Lin, Tsung-Mu Lai
  • Publication number: 20090065908
    Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.
    Type: Application
    Filed: October 20, 2008
    Publication date: March 12, 2009
    Inventors: Chia-Hua Chang, Huaa-Shu Wu, Tsung-Mu Lai
  • Patent number: 7468327
    Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: December 23, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hua Chang, Hua-Shu Wu, Tsung-Mu Lai
  • Publication number: 20080296701
    Abstract: A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.
    Type: Application
    Filed: December 14, 2007
    Publication date: December 4, 2008
    Applicant: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho