Patents by Inventor Tsung-Mu Lai
Tsung-Mu Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7728396Abstract: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.Type: GrantFiled: March 9, 2007Date of Patent: June 1, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hua-Shu Wu, Tsung-Mu Lai, Ming-Chih Chang, Che-Rong Laing
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Publication number: 20100073985Abstract: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.Type: ApplicationFiled: November 30, 2009Publication date: March 25, 2010Applicant: EMEMORY TECHNOLOGY INC.Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho
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Publication number: 20100006924Abstract: A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region.Type: ApplicationFiled: July 11, 2008Publication date: January 14, 2010Applicant: EMEMORY TECHNOLOGY INC.Inventors: Hsin-Ming Chen, Shao-Chang Huang, Shih-Chen Wang, Tsung-Mu Lai, Ming-Chou Ho, Chrong-Jung Lin
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Publication number: 20100002344Abstract: A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.Type: ApplicationFiled: July 2, 2008Publication date: January 7, 2010Inventors: Shao-Chang Huang, Wei-Yao Lin, Tsung-Mu Lai
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Publication number: 20090065908Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.Type: ApplicationFiled: October 20, 2008Publication date: March 12, 2009Inventors: Chia-Hua Chang, Huaa-Shu Wu, Tsung-Mu Lai
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Patent number: 7468327Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.Type: GrantFiled: June 13, 2006Date of Patent: December 23, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hua Chang, Hua-Shu Wu, Tsung-Mu Lai
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Publication number: 20080296701Abstract: A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.Type: ApplicationFiled: December 14, 2007Publication date: December 4, 2008Applicant: eMemory Technology Inc.Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho
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Publication number: 20080194076Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.Type: ApplicationFiled: February 12, 2007Publication date: August 14, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fa-Yuan Chang, Tsung-Mu Lai, Kai-Chih Liang, Hua-Shu Wu, Chin-Hsiung Ho, Gwo-Yuh Shiau, Chu-Wei Chang, Ming-Chyi Liu, Yuan-Chih Hsieh, Chia-Shiung Tsai, Nick Y. M. Shen, Ching-Chung Pai
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Publication number: 20070287213Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.Type: ApplicationFiled: June 13, 2006Publication date: December 13, 2007Inventors: Chia-Hua Chang, Hua-Shu Wu, Tsung-Mu Lai
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Patent number: 7295374Abstract: A method of manufacturing a micro-lens is disclosed. The method includes providing a convex photoresist surface, forming a lens mold on the convex photoresist surface, removing the lens mold from the convex photoresist surface, forming a micro-lens in the lens mold and removing the micro-lens from the lens mold.Type: GrantFiled: February 25, 2005Date of Patent: November 13, 2007Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Ming-Chih Chang, Hua-Shu Wu, Tsung-Mu Lai
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Patent number: 7255425Abstract: An ink-ejection unit of an inkjet printhead integrates an ink-channel wafer onto a CMOS wafer with a heating element fabricated therein. A nozzle film with a nozzle orifice is formed on the backside of the CMOS wafer, which allows two-dimensional ink ejecting from the backside of the CMOS wafer.Type: GrantFiled: December 2, 2004Date of Patent: August 14, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Mu Lai, Hua-Shu Wu, Ming-Chih Chang
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Publication number: 20070145366Abstract: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate . A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.Type: ApplicationFiled: March 9, 2007Publication date: June 28, 2007Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hua-Shu Wu, Tsung-Mu Lai, Ming-Chih Chang, Che-Rong Laing
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Patent number: 7198975Abstract: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.Type: GrantFiled: December 21, 2004Date of Patent: April 3, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hua-Shu Wu, Tsung-Mu Lai, Ming-Chih Chang, Che-Rong Laing
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Publication number: 20060193054Abstract: A method of manufacturing a micro-lens is disclosed. The method includes providing a convex photoresist surface, forming a lens mold on the convex photoresist surface, removing the lens mold from the convex photoresist surface, forming a micro-lens in the lens mold and removing the micro-lens from the lens mold.Type: ApplicationFiled: February 25, 2005Publication date: August 31, 2006Inventors: Ming-Chih Chang, Hua-Shu Wu, Tsung-Mu Lai
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Publication number: 20060189023Abstract: A method of making a MEMS device including providing a first substrate with an insulator layer thereon. A holder is attached to the insulator layer, and the first substrate is thinned. Thereafter, cavities are formed in the first substrate and the first substrate is flipped over and bonded to an integrated circuit wafer with the cavities facing the integrated circuit wafer. The holder is removed to provide a first substrate with cavities formed therein facing the integrated circuit wafer and an insulator layer overlying the first substrate.Type: ApplicationFiled: February 23, 2005Publication date: August 24, 2006Inventors: Fa-Yuan Chang, Hua-Shu Wu, Tsung-Mu Lai, Chau-Yang Wu
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Publication number: 20060131697Abstract: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.Type: ApplicationFiled: December 21, 2004Publication date: June 22, 2006Inventors: Hua-Shu Wu, Tsung-Mu Lai, Ming-Chih Chang, Che-Rong Laing
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Publication number: 20060119662Abstract: An ink-ejection unit of an inkjet printhead integrates an ink-channel wafer onto a CMOS wafer with a heating element fabricated therein. A nozzle film with a nozzle orifice is formed on the backside of the CMOS wafer, which allows two-dimensional ink ejecting from the backside of the CMOS wafer.Type: ApplicationFiled: December 2, 2004Publication date: June 8, 2006Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Mu Lai, Hua-Shu Wu, Ming-Chih Chang
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Patent number: 6573188Abstract: Within a method for selectively etching a second silicon layer with respect to a first silicon layer upon which is formed the second silicon layer there is employed an etch detection layer interposed between a first region of the first silicon layer and the second silicon layer, but not a second region of the first silicon layer and the second silicon layer. The etch detection layer provides for enhanced endpoint detection when selectively etching the second silicon layer with respect to the first silicon layer.Type: GrantFiled: May 9, 2002Date of Patent: June 3, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Tsung-Mu Lai, Hua-Shu Wu, Wan-Sheng Tseng