Patents by Inventor Tsung Wang

Tsung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110153284
    Abstract: A design method for integrating an embedded device into a liquid crystal panel is disclosed, including providing an adjustable backlight spectrum range, and determining an area ratio of sub pixels occupied by an embedded element and a readout line in a touch panel according to the adjustable backlight spectrum range.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 23, 2011
    Inventors: Heng-Hsien Li, Ming-Tsung Wang, Yang-Hui Chang, Shen-Tai Liaw, Naejye Hwang
  • Patent number: 7933575
    Abstract: The present invention discloses a circuit for settling DC offset and controlling RC time-constant in a direct conversion receiver. The circuit includes a variable resistive unit for providing a continuously or non-continuously variable resistance in the direct conversion receiver. The variable resistive unit can provide the variable resistance by utilizing a controllable transistor or a plurality of resistors. Accordingly, the variable resistive unit can be coupled to a capacitor for constituting a high pass filter, which is capable of rapidly settling DC offset in a direct conversion receiver.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: April 26, 2011
    Assignee: Mediatek, Inc.
    Inventors: Yuan-hung Chung, Chia-hsin Wu, Shou-tsung Wang
  • Patent number: 7929068
    Abstract: A pixel structure including a substrate, a scan line, a data line, a first and a second switching device, a first and a second pixel electrode, a first and a second bended pixel electrode, a first and a second connecting conductive layer, and a first and a second common line is provided. The scan line and data line demarcate a first and a second areas on the substrate, and the scan line is located between the two areas. The first and second switching devices are electrically connected to the scan line and the data line and are also electrically connected to the first and second pixel electrodes on the first and second areas respectively. The first and second bended pixel electrodes on the second and first areas are electrically connected to the first and second pixel electrodes through the first and second connecting conductive layers on the scan line respectively.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: April 19, 2011
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Yueh-Ping Chang, Chih-Chung Liu, Ming-Tsung Wang, Ming-Hsuan Chang
  • Patent number: 7916235
    Abstract: A pixel structure suitable for being disposed on a substrate includes a thin film transistor (TFT), a first pixel electrode, a second pixel electrode, a scan line and a data line. The TFT disposed on the substrate includes a gate, a source, a first drain and a second drain. A main TFT is formed by the gate, the source and the first drain. A sub-thin film transistor (sub-TFT) is formed by the gate, the first drain and the second drain. The first pixel electrode is electrically connected to the first drain, and a portion of the first drain extends between the second pixel electrode and the substrate to form capacitor-coupling electrode. The second pixel electrode is electrically connected to the second drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: March 29, 2011
    Assignee: Chunghwa Picture Tubes, Ltd
    Inventors: Ming-Tsung Wang, Chih-Chung Liu, Yueh-Ping Chang, Meng-Chieh Tai
  • Patent number: 7830486
    Abstract: A pixel structure suitable for being disposed on a substrate is provided. The pixel structure includes a scan line, a data line, a thin film transistor (TFT), a primary pixel electrode, and at least one secondary pixel electrode. The scan line and the data line are disposed on the substrate. The TFT is disposed on the substrate and is electrically connected to the scan line and the data line. The primary pixel electrode is electrically connected to a drain electrode of the TFT through a contact hole. The secondary pixel electrode is disposed above the drain electrode and the drain electrode is electrically coupled to the secondary pixel electrode. Besides, a liquid crystal display (LCD) panel having the pixel structure is also provided.
    Type: Grant
    Filed: September 29, 2007
    Date of Patent: November 9, 2010
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Chih-Chung Liu, Ming-Tsung Wang, Yueh-Ping Chang
  • Patent number: 7825914
    Abstract: A trigger operated portable electronic device is provided. A user only needs to insert a touch pen having a first metal contact into a touch pen receiving slot having second metal contacts. When the first metal contact is electrically coupled to the second metal contacts, the portable electronic device can be triggered to perform corresponding operating procedures. Thus, the convenience of operating the portable electronic device is improved.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: November 2, 2010
    Assignees: Giga-Byte Communications, Inc., Giga-Byte Technology Co., Ltd.
    Inventors: Chih-Chiang Huang, Cheng Yao, Chung-Tsung Wang
  • Patent number: 7816233
    Abstract: The invention provides a method of manufacturing a composite wafer structure. In particular, the method, according to the invention, is based on the fracture mechanics theory to actively control fracture induced during the manufacture of the composite wafer structure and to further protect from undesired edge damage. Thereby, the method, according to the invention, can enhance the yield rate of industrial mass production regarding the composite wafer structure.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: October 19, 2010
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Jer-Liang Yeh, Jing-Yi Huang, Wen-Ching Hsu, Ya-Lan Ho, Sung-Lin Hsu, Jung-Tsung Wang
  • Publication number: 20100237350
    Abstract: A pixel structure suitable for being disposed on a substrate includes a thin film transistor (TFT), a first pixel electrode, a second pixel electrode, a scan line and a data line. The TFT disposed on the substrate includes a gate, a source, a first drain and a second drain. A main TFT is formed by the gate, the source and the first drain. A sub-thin film transistor (sub-TFT) is formed by the gate, the first drain and the second drain. The first pixel electrode is electrically connected to the first drain, and a portion of the first drain extends between the second pixel electrode and the substrate to form capacitor-coupling electrode. The second pixel electrode is electrically connected to the second drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.
    Type: Application
    Filed: June 4, 2010
    Publication date: September 23, 2010
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Ming-Tsung Wang, Chih-Chung Liu, Yueh-Ping Chang, Meng-Chieh Tai
  • Patent number: 7760003
    Abstract: The present invention sets forth a controllable resistive circuit which comprises a transistor, a capacitor, a charging unit and a discharging unit. The transistor is capable of providing a variable resistance which is controlled to vary continuously and smoothly. The charging and discharging units are used to respectively charge and discharge the capacitor in different periods. As a result, the capacitor can provide a variable voltage which is controlled to vary continuously and smoothly to control the equivalent resistance of the transistor during the period the capacitor is discharging. Therefore, the controllable resistive circuit in accordance with the present invention is capable of being used in any kind of circuit which requires a variable resistance varied continuously and smoothly.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: July 20, 2010
    Assignee: MEDIATEK Inc.
    Inventors: Chia-hsin Wu, Shou-tsung Wang, Yuan-hung Chung
  • Patent number: 7755710
    Abstract: A pixel structure includes a gate, a source, a first drain, a second drain, a third drain, a first pixel electrode, a second pixel electrode, a scan line and a data line. The gate, the source and the first drain form a first thin film transistor. The gate, the source and the second drain form a second thin film transistor. The gate, the second drain and the third drain form a sub-thin film transistor (sub-TFT). Additionally, the first pixel electrode is electrically connected to the first drain, and the second drain extends to a portion between the second pixel electrode and the substrate such that a capacitor-coupling electrode is formed. Moreover, the second pixel electrode is electrically connected to the third drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.
    Type: Grant
    Filed: August 19, 2007
    Date of Patent: July 13, 2010
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Ming-Tsung Wang, Chih-Chung Liu, Yueh-Ping Chang, Meng-Chieh Tai
  • Publication number: 20100141861
    Abstract: A pixel structure is provided. The pixel structure includes a scan line, a gate, a first dielectric layer, a channel layer, a source, a drain, a data line, a second dielectric layer, and a pixel electrode. The gate is electrically connected to the scan line and has a first notch. The first dielectric layer covers the scan line and the gate. The channel layer is disposed on the first dielectric layer over the gate and exposed by the first notch. The source and the drain are disposed on the channel layer. Part of the drain is located over the first notch. The data line is disposed on the first dielectric layer and electrically connected to the source. The second dielectric layer covers the source, the drain and the data line. The pixel electrode is disposed on the second dielectric layer and electrically connected to the drain.
    Type: Application
    Filed: February 10, 2010
    Publication date: June 10, 2010
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Ming-Tsung Wang, Ming-Hsuan Chang, Zhi-Zhong Liu, Meng-Chieh Tai
  • Patent number: 7688392
    Abstract: A pixel structure is provided. The pixel structure includes a scan line, a gate, a first dielectric layer, a channel layer, a source, a drain, a data line, a second dielectric layer, and a pixel electrode. The gate is electrically connected to the scan line and has a first notch. The first dielectric layer covers the scan line and the gate. The channel layer is disposed on the first dielectric layer over the gate and exposed by the first notch. The source and the drain are disposed on the channel layer. Part of the drain is located over the first notch. The data line is disposed on the first dielectric layer and electrically connected to the source. The second dielectric layer covers the source, the drain and the data line. The pixel electrode is disposed on the second dielectric layer and electrically connected to the drain.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: March 30, 2010
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Ming-Tsung Wang, Ming-Hsuan Chang, Zhi-Zhong Liu, Meng-Chieh Tai
  • Patent number: 7679869
    Abstract: An input/output device comprises a bonding pad, a signal transport circuit, and a blocking unit. The signal transport circuit has a first terminal connected to the bonding pad and a second terminal connected to a core circuit of an IC product. The signal transport circuit is capable of transporting a signal either from the bonding pad to the core circuit or from the core circuit to the bonding pad. The blocking unit has a control terminal and is coupled between the bonding pad and the signal transport circuit. The control terminal is coupled to receive an enable signal. The blocking unit ties the bonding pad to a predetermined voltage level when the enable signal is de-asserted, thereby blocking the signal transport provided by the signal transport circuit. The blocking unit unties the bonding pad from the predetermined voltage level when the enable signal is asserted.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: March 16, 2010
    Assignee: Mediatek Inc.
    Inventors: Bing-Jye Kuo, Shou-Tsung Wang, Po-Sen Tseng, Chih-Chun Tang, Shin-Fu Chen
  • Publication number: 20090212839
    Abstract: The present invention discloses a circuit for settling DC offset and controlling RC time-constant in a direct conversion receiver. The circuit includes a variable resistive unit for providing a continuously or non-continuously variable resistance in the direct conversion receiver. The variable resistive unit can provide the variable resistance by utilizing a controllable transistor or a plurality of resistors. Accordingly, the variable resistive unit can be coupled to a capacitor for constituting a high pass filter, which is capable of rapidly settling DC offset in a direct conversion receiver.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 27, 2009
    Applicant: MEDIATEK, INC.
    Inventors: Yuan-hung Chung, Chia-hsin Wu, Shou-tsung Wang
  • Publication number: 20090191343
    Abstract: A method for forming a decorative member includes applying a resilient layer onto a basic layer, applying a printing layer onto the resilient layer, applying another resilient layer onto the printing layer for forming a layered element, forming the layered element into a three-dimensional element, shaping the three-dimensional element into a prototype, and applying a protective layer onto the prototype for covering and shielding and protecting the prototype. The layered element may be disposed in a mold device for heating and vacuumming the layered element, or may be disposed between two mold pieces of a mold device for being formed into the three-dimensional element with the mold pieces of the mold device.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Inventor: Ming Tsung Wang
  • Patent number: 7567787
    Abstract: An apparatus and method for internally calibrating a direct conversion receiver (DCR) through feeding a calibration signal via ESD protection circuitry is disclosed. The apparatus includes an internal signal generator for generating a calibration signal, a front-end input stage for receiving an RF signal at an input node, an ESD protection unit for protecting against electrostatic discharge, and a switch unit coupled to the ESD protection unit, for selectively passing a calibration signal to the front-end input stage, whereby the connection of the switch unit and the ESD protection unit means that when the DCR is operating in normal mode, the switch unit will not affect the noise performance and matching of the receiver.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: July 28, 2009
    Assignee: MediaTek Inc.
    Inventors: Bing-Jye Kuo, Shou-Tsung Wang
  • Publication number: 20090134455
    Abstract: A semiconductor device including a substrate, a first well, a second well, a gate, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the substrate. The gate is formed on the substrate and overlaps the first and the second wells. The first doped region includes the second conductive type. The first doped region is formed in the first well and self-aligned with the gate. The second doped region includes the second conductive type. The second doped region is formed in the second well and self-aligned with the gate. The gate, the first and the second doped regions constitute a transistor.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 28, 2009
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shih-Fang Lin, Meng-Yen Hsieh, Yi-Tsung Jan, Sung-Min Wei, Chia-Yi Lee, Chun-Yao Li, Han-Lung Tsai, Zhe-Xiong Wu, Wen-Tsung Wang
  • Patent number: 7508277
    Abstract: The invention provides a phase-locked loop (PLL). Since a loop bandwidth of the PLL is a function of a gain of a phase detector and a gain of a voltage controlled oscillator (VCO), by adjusting the gain of the phase detector, the variation of the gain of the VCO (i.e., the tuning sensitivity) is compensated, so that the loop bandwidth of the PLL becomes more stable.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: March 24, 2009
    Assignee: MediaTek Inc.
    Inventors: Chang-Fu Kuo, Po-Sen Tseng, Shou-Tsung Wang, Ling-Wei Ko
  • Publication number: 20090060483
    Abstract: An underwater monitoring system with an automatic cleaning capability includes abase, a monitoring device mounted on the base, and a water-flow forming device mounted on the base and operable to form and direct a water flow toward the monitoring device for cleaning the monitoring device. The water-flow forming device includes a pressurizing pump for forming the water flow, such as a laminar flow, and a controller coupled electrically to the pressurizing pump for controlling activation and deactivation of the pressurizing pump.
    Type: Application
    Filed: December 27, 2007
    Publication date: March 5, 2009
    Applicant: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Kuen-Yu Huang, Yao-Tsung Wang, Fang-Pang Lin, Jo-Yu Chang
  • Patent number: 7496798
    Abstract: Health management of machines and/or equipment, such as gas turbine engines, airplanes, and industrial equipment using a model centric method.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: February 24, 2009
    Inventors: Jaw Link, Yu-tsung Wang, George Mink, Hoang Tran Van, Yi-hua He