Patents by Inventor Tsung Wang

Tsung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6031766
    Abstract: A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: February 29, 2000
    Assignee: Macronix International Co., Ltd.
    Inventors: Chia-Shing Chen, Mam-Tsung Wang, Wenpin Lu, Ming-Hung Chou, Ying-Che Lo, Ming-Shang Chen
  • Patent number: 6028790
    Abstract: A method and apparatus for programming a non-volatile memory cell wherein the rate of current flowing through the cell is controlled via a current limiter coupled to the source node of the memory cell. The rate of current through the current limiter controls the programming current rate through the memory cell. The current limiter is controlled by an input which is dependant upon the setting of a current through an associated current mirror device. The current mirror current is controlled by a pre-defined input condition on a current source. The mirror current is used by a biasing circuit to generate a proportional input to the current limiter device. The current source thereby controls the current limiter rate. The current source can be formed from the same process as the memory cells and its output will thereby vary with the conductivity of the formed devices.
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: February 22, 2000
    Assignee: Macronix International Co., Ltd.
    Inventors: Chin-Hsi Lin, Ful-Long Ni, Mam-Tsung Wang
  • Patent number: 5963808
    Abstract: A memory cell having an asymmetric source and drain connection to buried bit-lines providing a Fowler-Nordheim tunneling region and a non-tunneling region defined by a bird's beak encroachment on each of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single bit-line.
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: October 5, 1999
    Assignee: Macronix International Co., Ltd.
    Inventors: Wenpin Lu, Tao-Cheng Lu, Mam-Tsung Wang
  • Patent number: 5959892
    Abstract: The present invention provides a method and an apparatus for programming a selected call within a virtual ground EPROM array cell without disturbing adjacent array cells.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: September 28, 1999
    Assignee: Macronix International Co., Ltd.
    Inventors: Chin-Hsi Lin, Shi-Charng Ai, Chien-Sing Lee, Ful-Long Ni, Mam-Tsung Wang, Chin-Yi Huang
  • Patent number: 5912845
    Abstract: A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: June 15, 1999
    Assignee: Macronix International Co., Ltd.
    Inventors: Chia-Shing Chen, Mam-Tsung Wang, Wenpin Lu, Ming-Hung Chou, Ying-Che Lo, Ming-Shang Chen
  • Patent number: 5912844
    Abstract: Method for writing data to a NOR-type flash memory array including loading page data to a bit-latch buffer, programming cells to low threshold voltage V.sub.t, and programming cells to high V.sub.t. Programming cells to high V.sub.t by either: Channel Hot Electron Injection (CHEI) or Source Side Injection (SSI). CHEI releases the band-to-band induced hot hole damage while SSI further reduces the sector size to be the same as page size for NOR-type flash EEPROM memory.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: June 15, 1999
    Assignee: Macronix International Co., Ltd.
    Inventors: Chia-Shing Chen, Mam-Tsung Wang
  • Patent number: 5895241
    Abstract: A mask read-only-memory cell structure without ROM code implantation is presented. By using double polysilicon technology, ROM code cells which store data "0" can be replaced by cells with double polysilicon layers and an insulating layer between them. Normal cells with double polysilicon layers but without an insulating layer between them form normal cells store data "1". According to the invention, further scaling of mask ROM is possible and operating condition can be released because of high junction breakdown voltage. Furthermore, the double polysilicon technology makes redundancy circuit more easily to implement.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: April 20, 1999
    Inventors: Tao Cheng Lu, Mam-Tsung Wang
  • Patent number: 5893738
    Abstract: A semiconductor mask-programmable read-only-memory array structure provides double density storage of data information by means of thin film memory cell transistors formed on both sides of a layer of thin film polysilicon. At a bottom surface of a layer of thin film polysilicon which has a bottom gate oxide grown thereon, a plurality of polysilicon bottom cell wordlines intersects a plurality of bitlines to form an array of bottom cell memory transistors. The bitlines are heavily-doped diffusion regions within the layer thin film polysilicon. Additionally, a top surface of the layer of thin film polysilicon has a top gate oxide grown thereon. Over this top gate oxide, a plurality of polysilicon top cell wordlines intersects the plurality of bitlines to form an array of top cell memory transistors, thereby producing a NOR-type read-only-memory array structure with double the storage density of conventional, prior art structures.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: April 13, 1999
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Ju Chen, Mam-Tsung Wang
  • Patent number: 5889146
    Abstract: This invention is a novel synthesis of BCA-peptides (BCA: bifunctional chelating agents). In this method, the starting material--Fmoc-Thr(ol)-Terephthal-Acetal-Amide Resin is coupled with the various amino acids. The straight peptide-resin of D-Phe-Cys(Trt)-Phe-D-Trp(Boc)-Lys(Boc)-Thr(tBu)-Cys(Trt)-Thr(ol)-Terephtha l-Acetal-Amide Resin was obtained. This compound reacted with iodine to give disulfide-containing peptide resin of ##STR1## Cleavage of the peptide from the resin was achieved by TFA. The cleavaged peptide was protected by the reaction of octreotide with di-t-butyldicarbonate. BCA was coupled to the selectively protected octreotide. This product was obtained by reaction of protected BCA-peptides with TFA. The final product was labeled by radioisotope .sup.111 InCl.sub.3 for tumor imaging radiopharmaceuticals.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: March 30, 1999
    Assignee: Institute Of Nuclear Energy Research
    Inventors: Te-Wei Lee, Shui-Tein Chen, Shiang-Rong Chang, Shyh-Yi Chyi, Chang-Mau Shing, Tian-Fu Huang, Lie-Hang Shen, Zei-Tsan Tsai, Kung-Tsung Wang, Gann Ting
  • Patent number: 5837584
    Abstract: A memory cell having asymmetrically placed source and drain diffusions which allows programming and erasure to be obtained across one of the source or drain diffusions which extends furthest beneath the floating gate while minimizing electron tunneling at the other of the source or drain diffusions which extends only minimally beneath the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit-line.
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: November 17, 1998
    Assignee: Macronix International Co., Ltd.
    Inventors: Wenpin Lu, Mam-Tsung Wang
  • Patent number: 5831116
    Abstract: A process for partially oxidizing alcohols such as methanol, comprising the steps of a) introducing into a reactor unit containing a solid acid catalyst amounts of alcohol and oxygen; and a supercritical fluid (such as SCF CO.sub.2) mobile phase; and b) partially oxidizing the alcohol to its corresponding ether, aldehyde, ester or acid. In an advantageous embodiment, methanol is oxidized using an aerogel acid catalyst to produce methyl ether.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: November 3, 1998
    Assignee: Northeastern University
    Inventors: Chien-Tsung Wang, Ronald J. Willey
  • Patent number: 5828113
    Abstract: A semiconductor mask-programmable read-only-memory array structure provides double density storage of data information by means of thin film memory cell transistors formed on both sides of a layer of thin film polysilicon. At a bottom surface of a layer of thin film polysilicon which has a bottom gate oxide grown thereon, a plurality of polysilicon bottom cell wordlines intersects a plurality of bitlines to form an array of bottom cell memory transistors. The bitlines are heavily-doped diffusion regions within the layer thin film polysilicon. Additionally, a top surface of the layer of thin film polysilicon has a top gate oxide grown thereon. Over this top gate oxide, a plurality of polysilicon top cell wordlines intersects the plurality of bitlines to form an array of top cell memory transistors, thereby producing a NOR-type read-only-memory array structure with double the storage density of conventional, prior art structures.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: October 27, 1998
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Ju Chen, Mam-Tsung Wang