Method and circuit for substrate current induced hot e.sup.- injection (SCIHE) approach for V.sub.T convergence at low V.sub.CC voltage
A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
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Claims
1. A method for correcting an over-erase condition within a non-volatile memory array, comprising:
- providing a non-volatile memory array having a plurality of single transistor memory cells, each memory cell comprising a stacked pair of control and floating gates spaced above a channel region interposed between a source and drain region; and
- applying a first voltage to the control gate, an active current limiter to the source region, a non-positive voltage to the channel region, and a positive voltage to the drain region.
2. The method as recited in claim 1, wherein said providing step comprises patterning the stacked pair of control and floating gates from a stacked pair of polysilicon layers having a dielectric layer interposed therebetween.
3. The method as recited in claim 1, wherein said channel region comprises a portion of a single crystalline substrate material, wherein said portion is adapted to receive a non-positive voltage.
4. The method as recited in claim 1, wherein said non-positive voltage is a voltage having an absolute magnitude greater than 0.5.
5. The method as recited in claim 1, wherein said non-positive voltage is a voltage having an absolute magnitude greater than 1.
6. The method as recited in claim 1, wherein said positive voltage is a voltage having an absolute magnitude less than 5.
7. The method as recited in claim 1, wherein said positive voltage is a voltage having an absolute magnitude less than 4.5.
8. The method as recited in claim 1, wherein said first voltage is between -1 V and 6 V.
9. The method as recited in claim 1, wherein the active current limiter is a current mirror.
10. The method as recited in claim 1, wherein the active current limiter is an NMOSFET operating at saturation mode.
11. The method as recited in claim 1, wherein the active current limiter is a current source.
12. The method as recited in claim 1, wherein the active current limiter provides current in a range of 1.5 mA to 1.2 mA per 512 K memory cells.
13. The method as recited in claim 1, as a result of said applying step, inducing electrons onto said floating gate for neutralizing positive charge thereon.
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Type: Grant
Filed: Sep 10, 1997
Date of Patent: Jun 15, 1999
Assignee: Macronix International Co., Ltd. (Taipei)
Inventors: Chia-Shing Chen (Hsin Chu), Mam-Tsung Wang (Hsin Chu), Wenpin Lu (E-Lan), Ming-Hung Chou (Miao-Li), Ying-Che Lo (Tainan), Ming-Shang Chen (Hsing Chu)
Primary Examiner: David Nelms
Assistant Examiner: Tuan T. Nguyen
Law Firm: Haynes & Beffel LLP
Application Number: 8/926,554
International Classification: G11C 1604;
