Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

Abstract: A high voltage depletion mode MOS device with adjustable threshold voltage includes: a first conductive type well region; a second conductive type channel region, wherein when the channel region is not depleted, the MOS device is conductive, and when the channel region is depleted, the MOS device is non-conductive; a second conductive type connection region which contacts the channel region; a first conductive type gate, for controlling the conductive condition of the MOS device; a second conductive type lightly doped diffusion region formed under a spacer layer of the gate and contacting the channel region; a second type source region; and a second type drain region contacting the connection region but not contacting the gate; wherein the gate has a first conductive type doping or both a first and a second conductive type doping, and wherein a net doping concentration of the gate is determined by a threshold voltage target.

Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a first deep well, a second deep well, a drift well, a first well, a second well, a body region, a body contact, a high voltage well, a gate, and a source and a drain. The high voltage well is formed in the second deep well, and the high voltage well is not in contact with any of the first deep well, the first well, and the second well, wherein at least part of the high voltage well is located right below all of a drift region to suppress a latch-up current generated in the high voltage device.

Abstract: A high-voltage semiconductor device integrates a MOS transistor with a Schottky barrier diode. The MOS transistor has a semiconductor substrate of a first conduction type, a well of a second conduction, a body of the first conduction type, and a doped source of the second type. A control gate formed above the body controls electric connection between the doped source and the well. The Schottky barrier diode has a metal, functioning to be an anode of the Schottky barrier diode and contacting the well to form a Schottky barrier junction therebetween.

Abstract: An N-type high voltage device includes: a semiconductor layer, a well region, a floating region, a bias region, a body region, a body contact, a gate, a source and a drain. The floating region and the bias region both have P-type conductivity, and both are formed in a drift region in the well region. The bias region is electrically connected with a predetermined bias voltage, and the floating region is electrically floating, to increase a breakdown voltage of the high voltage device and to suppress turning-ON a parasitic transistor in the high voltage device.

Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.

Abstract: A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a body contact, a buffer region, a gate, and a source and a drain. The body contact includes a main body contact and at least one sub-body contact. The main body contact is adjacent to the source, wherein the main body contact and the source are rectangles that extend along a width direction, and the source is located between the main body contact and the gate. The sub-body contact extends from the main body contact toward the gate and contacts an inverse current channel. The buffer region encompasses all the periphery of the body region below a top surface of the semiconductor layer, wherein an impurity concentration of the buffer region is lower than an impurity concentration of the body region.

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, a drain and a conductive connection structure. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region in the operation region. The sub-gate is a rectangle shape extending along a width direction, and in parallel with the gate. A conductive connection structure connects the gate and the sub-gate.

Abstract: A high voltage device for use as a lower switch in a power stage of a switching regulator includes at least one lateral diffused metal oxide semiconductor (LDMOS) device and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well, a body region, a gate, a source, and a drain. The SBD includes a Schottky metal layer and a Schottky semiconductor layer. The Schottky metal layer is electrically connected to the source, and the Schottky semiconductor layer is in contact with the well.

Abstract: A manufacturing method of a junction field effect transistor (JFET) includes: providing a substrate having a first conductivity type, forming a channel region having a second conductive type, forming a field region having the first conductivity type, forming a gate having the first conductivity type, forming a source having the second conductive type, forming a drain having the second conductive type, and forming a lightly doped region having the second conductive type. The channel region is formed by a first ion implantation process step, and the lightly doped region is formed by a second ion implantation process step. The second ion implantation process step implants first conductivity type impurities into a part of the channel region.

Abstract: A metal oxide semiconductor (MOS) device includes: a semiconductor layer, an isolation structure, a well, a gate, a source, a drain, a first lightly doped region, and a second lightly doped region. The first lightly doped region is located right below a spacer layer and a portion of a dielectric layer of the gate. In a channel direction, the first lightly doped region is between and contacts the drain and an inversion current channel. The second lightly doped region includes a first part and a second part. The first part is located right below the spacer which is near the source, and the first part is between and contacts the source and the inversion current channel. The second part is located right below the spacer which is near the drain, and the second part is between and contacts the drain and the first lightly doped region.

Abstract: A high voltage MOS device includes: a well, a drift region, a gate, a source, a drain, and plural buried columns. A part of the gate is stacked on a part of the well, and another part of the gate is stacked on a part of the drift region. The source connects the well in a lateral direction. The drain connects the drift region in the lateral direction. The drain and the source are separated by the well and the drift region, and the drain and the source are located at different sides of the gate. The plural buried columns are formed beneath the top surface by a predetermined distance, and each buried column does not connect the top surface. At least a part of every buried column is surrounded by the drift region, and the buried columns and the drift region are arranged in an alternating manner.

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, a drift oxide region, and a top region. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a first trench bottom surface of the first trench. The top region is formed in the well right below the drift oxide region, and is in contact with the drift oxide region.

Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.

Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semiconductor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.