Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a body contact, a buffer region, a gate, and a source and a drain. The body contact includes a main body contact and at least one sub-body contact. The main body contact is adjacent to the source, wherein the main body contact and the source are rectangles that extend along a width direction, and the source is located between the main body contact and the gate. The sub-body contact extends from the main body contact toward the gate and contacts an inverse current channel. The buffer region encompasses all the periphery of the body region below a top surface of the semiconductor layer, wherein an impurity concentration of the buffer region is lower than an impurity concentration of the body region.

Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device and a manufacturing method thereof. The MOS device includes: a semiconductor substrate, a gate, a source, a drain, and two LDDs (Lightly-Doped-Drains). At least one recess is formed at an upper surface of the semiconductor substrate. The recess has a depth which is deeper than the depth of the two LDDs. The recess is filled with a conductive material. A vertical connection portion is formed at a boundary of the recess in the vertical direction, to at least connect one of the LDDs to the drain. The LDD closer to the drain is not laterally in contact with the drain but is connected to the drain by the vertical direction.

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes: a semiconductor layer, an isolation oxide region, a first drift oxide region, a second drift oxide region, a well region, a body region, a gate, a source, and a drain. The isolation oxide region, the first drift oxide region, and the second drift oxide region have an isolation thickness, a first thickness, and a second thickness respectively in a vertical direction, wherein the second thickness is less than the first thickness. The second drift oxide region is a chemical vapor deposition (CVD) oxide region, and is formed by a CVD process step. The first drift oxide region is a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure.

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, a drain and a conductive connection structure. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region in the operation region. The sub-gate is a rectangle shape extending along a width direction, and in parallel with the gate. A conductive connection structure connects the gate and the sub-gate.

Abstract: A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.

Abstract: A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.

Abstract: A high voltage device is formed in a semiconductor substrate, and includes: a first deep well, a lateral lightly doped region, a high voltage well, an isolation region, a body region, a gate, a source, a drain, and a first isolation well. The first deep well and the first isolation well are for electrical isolating the high voltage device from neighboring devices below a top surface of the semiconductor substrate. The lateral lightly doped region is located between the first deep well and the high voltage well in a vertical direction, and the lateral lightly doped region contacts the first deep well and the high voltage well. The lateral lightly doped region is for reducing an inner capacitance of the high voltage device when the high voltage device operates, to improve transient response.

Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device having mitigated threshold voltage roll-off and a threshold voltage roll-off mitigation method therefor. The MOS device includes: a substrate, a well region, an isolation region, a gate, two LDDs (Lightly-Doped-Drains), a source, a drain and a compensation doped region. The compensation doped region is substantially in contact with at least a part of a recessed portion along the channel length direction. Viewing from a cross-section view, at a boundary where the compensation doped region is in contact with the isolation region along the channel length direction, the compensation doped region has two doped region widths along the channel width direction, wherein, the two doped region widths of the compensation doped region are both not greater than 10% of the width of the operation region. Two doped region widths are defined as distances within an interior part and an exterior part of the operation region, respectively.

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, two buried regions. A PN junction is formed between the body region and the high voltage well, wherein the PN junction is perpendicular to a channel direction. One buried region is formed in the epitaxial layer and has a first conductive type, wherein an inner side boundary thereof is located between the drain and the PN junction. The other buried region is formed in the substrate and in the epitaxial layer and has a second conductive type, wherein an inner side boundary thereof is located between the drain and the PN junction. The impurity concentration of the second buried region is sufficient to prevent the high voltage well between the PN junction and the drain from being completely depleted when the high-side power device is ON.

Abstract: The invention provides a power device, which includes: an operation layer, including a top surface, a body region and a drift region, the body region and the drift region being connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region; a gate, formed on the top surface, and the PN junction is located under the gate; a source, formed in a portion of the operation layer between the body region and the top surface; a drain, formed in another portion of the operation layer between the drift region and the top surface; a first conduction portion, formed on the top surface for electrically connecting the source; a conduction layer, formed on the first conduction portion and electrically connected to the source via the first conduction portion; and a second conduction portion, formed on the top surface and between the conduction layer and the drift region in a thickness direction, for electrically connecting the drift region and the conductio

Abstract: A high voltage MOS device includes: a well, a drift region, a gate, a source, a drain, and plural buried columns. A part of the gate is stacked on a part of the well, and another part of the gate is stacked on a part of the drift region. The source connects the well in a lateral direction. The drain connects the drift region in the lateral direction. The drain and the source are separated by the well and the drift region, and the drain and the source are located at different sides of the gate. The plural buried columns are formed beneath the top surface by a predetermined distance, and each buried column does not connect the top surface. At least a part of every buried column is surrounded by the drift region, and the buried columns and the drift region are arranged in an alternating manner.

Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.

Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.

Abstract: A high voltage MOS device includes: a well region with a first conductive type, a body region with a second conductive type, a gate, plural source regions with the first conductive type, a drain region with the first conductive type, and a body contact region with the second conductive type. The plural source regions contact the gate, and are substantially arranged in parallel along a width direction, and each two neighboring source regions are not contacted with each other. The body connection region extends along the width direction and overlaps with at least two of the source regions, such that the body connection region includes at least a first region and a second region, wherein the first region overlaps with at least one of the source regions, and the second region does not overlap any of the regions. The contact region does not contact the gate along a lateral direction.

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

Abstract: A high voltage device is formed in a semiconductor substrate, and includes: a first deep well, a lateral lightly doped region, a high voltage well, an isolation region, a body region, a gate, a source, a drain, and a first isolation well. The first deep well and the first isolation well are for electrical isolating the high voltage device from neighboring devices below a top surface of the semiconductor substrate. The lateral lightly doped region is located between the first deep well and the high voltage well in a vertical direction, and the lateral lightly doped region contacts the first deep well and the high voltage well. The lateral lightly doped region is for reducing an inner capacitance of the high voltage device when the high voltage device operates, to improve transient response.

Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device and a manufacturing method thereof. The MOS device includes: a semiconductor substrate, a gate, a source, a drain, and two LDDs (Lightly-Doped-Drains). At least one recess is formed at an upper surface of the semiconductor substrate. The recess has a depth which is deeper than the depth of the two LDDs. The recess is filled with a conductive material. A vertical connection portion is formed at a boundary of the recess in the vertical direction, to at least connect one of the LDDs to the drain. The LDD closer to the drain is not laterally in contact with the drain but is connected to the drain by the vertical direction.

Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, two buried regions. A PN junction is formed between the body region and the high voltage well, wherein the PN junction is perpendicular to a channel direction. One buried region is formed in the epitaxial layer and has a first conductive type, wherein an inner side boundary thereof is located between the drain and the PN junction. The other buried region is formed in the substrate and in the epitaxial layer and has a second conductive type, wherein an inner side boundary thereof is located between the drain and the PN junction. The impurity concentration of the second buried region is sufficient to prevent the high voltage well between the PN junction and the drain from being completely depleted when the high-side power device is ON.