Patents by Inventor Tsung-Yi Huang

Tsung-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10680104
    Abstract: A metal oxide semiconductor (MOS) device includes: a semiconductor layer, an isolation structure, a well, a gate, a source, a drain, a first lightly doped region, and a second lightly doped region. The first lightly doped region is located right below a spacer layer and a portion of a dielectric layer of the gate. In a channel direction, the first lightly doped region is between and contacts the drain and an inversion current channel. The second lightly doped region includes a first part and a second part. The first part is located right below the spacer which is near the source, and the first part is between and contacts the source and the inversion current channel. The second part is located right below the spacer which is near the drain, and the second part is between and contacts the drain and the first lightly doped region.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 9, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Publication number: 20200119189
    Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, a drift oxide region, and a top region. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a first trench bottom surface of the first trench. The top region is formed in the well right below the drift oxide region, and is in contact with the drift oxide region.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 16, 2020
    Inventor: Tsung-Yi Huang
  • Patent number: 10622440
    Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 14, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Patent number: 10622473
    Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.
    Type: Grant
    Filed: August 19, 2018
    Date of Patent: April 14, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen, YU-Ting Yeh
  • Publication number: 20200111906
    Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semiconductor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.
    Type: Application
    Filed: August 13, 2019
    Publication date: April 9, 2020
    Inventors: Tsung-Yi Huang, Kun-Huang Yu, Ying-Shiou Lin, Chu-Feng Chen, Chung-Yu Hung, Yi-Rong Tu
  • Publication number: 20200105926
    Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.
    Type: Application
    Filed: August 15, 2019
    Publication date: April 2, 2020
    Inventors: Tsung-Yi Huang, Kun-Huang Yu
  • Patent number: 10600908
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a semiconductor substrate, and includes: a gate, a source, a drain, and at least one plug plate electrode. The plug plate electrode is in direct contact with the gate, and is electrically connected to the gate. The plug plate electrode extends downwards from the bottom of the gate to the semiconductor substrate, through a current vertical height of a conductive current when the high voltage is ON. The plug plate electrode is between the source and the drain in a lateral direction. The plug plate electrode includes a dielectric layer and a conductive layer.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: March 24, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 10600895
    Abstract: The invention provides a power device, which includes: an operation layer, including a top surface, a body region and a drift region, the body region and the drift region being connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region; a gate, formed on the top surface, and the PN junction is located under the gate; a source, formed in a portion of the operation layer between the body region and the top surface; a drain, formed in another portion of the operation layer between the drift region and the top surface; a first conduction portion, formed on the top surface for electrically connecting the source; a conduction layer, formed on the first conduction portion and electrically connected to the source via the first conduction portion; and a second conduction portion, formed on the top surface and between the conduction layer and the drift region in a thickness direction, for electrically connecting the drift region and the conductio
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: March 24, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Kuo-Hsuan Lo, Tsung-Yi Huang
  • Publication number: 20200066878
    Abstract: A MOS device has a reduced ON-resistance; the MOS device has a first lightly doped diffusion (LDD) region which is longer than a second LDD region thereof, and the impurity concentration of the second LDD region is higher than that of the first LDD region. Another MOS device has a spacer layer on a drain sidewall of the gate but does not have a spacer layer on a source sidewall of the gate, wherein the drain sidewall is a sidewall of the gate conductive layer that is adjacent to the drain, and the source sidewall is a sidewall of the gate conductive layer that is adjacent to the source. The MOS device has a higher breakdown voltage, lower ON-resistance, and mitigates the threshold voltage roll-off and other short channel effects.
    Type: Application
    Filed: June 20, 2019
    Publication date: February 27, 2020
    Inventor: Tsung-Yi Huang
  • Publication number: 20200052072
    Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a first deep well, a second deep well, a drift well, a first well, a second well, a body region, a body contact, a high voltage well, a gate, and a source and a drain. The high voltage well is formed in the second deep well, and the high voltage well is not in contact with any of the first deep well, the first well, and the second well, wherein at least part of the high voltage well is located right below all of a drift region to suppress a latch-up current generated in the high voltage device.
    Type: Application
    Filed: July 4, 2019
    Publication date: February 13, 2020
    Inventor: Tsung-Yi Huang
  • Publication number: 20200044022
    Abstract: A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.
    Type: Application
    Filed: June 22, 2019
    Publication date: February 6, 2020
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Publication number: 20200006490
    Abstract: An N-type high voltage device includes: a semiconductor layer, a well region, a floating region, a bias region, a body region, a body contact, a gate, a source and a drain. The floating region and the bias region both have P-type, and both are formed in a drift region in the well region. The bias region is electrically connected with a predetermined bias voltage, and the floating region is electrically floating, to increase a breakdown voltage of the high voltage device and suppressing turning-ON a parasitic transistor in the high voltage device.
    Type: Application
    Filed: March 14, 2019
    Publication date: January 2, 2020
    Inventor: Tsung-Yi Huang
  • Publication number: 20190393346
    Abstract: A metal oxide semiconductor (MOS) device includes: a semiconductor layer, an isolation structure, a well, a gate, a source, a drain, a first lightly doped region, and a second lightly doped region. The first lightly doped region is located right below a spacer layer and a portion of a dielectric layer of the gate. In a channel direction, the first lightly doped region is between and contacts the drain and an inversion current channel. The second lightly doped region includes a first part and a second part. The first part is located right below the spacer which is near the source, and the first part is between and contacts the source and the inversion current channel. The second part is located right below the spacer which is near the drain, and the second part is between and contacts the drain and the first lightly doped region.
    Type: Application
    Filed: March 13, 2019
    Publication date: December 26, 2019
    Inventor: Tsung-Yi Huang
  • Publication number: 20190378924
    Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a body contact, a buffer region, a gate, and a source and a drain. The body contact includes a main body contact and at least one sub-body contact. The main body contact is adjacent to the source, wherein the main body contact and the source are rectangles that extend along a width direction, and the source is located between the main body contact and the gate. The sub-body contact extends from the main body contact toward the gate and contacts an inverse current channel. The buffer region encompasses all the periphery of the body region below a top surface of the semiconductor layer, wherein an impurity concentration of the buffer region is lower than an impurity concentration of the body region.
    Type: Application
    Filed: March 13, 2019
    Publication date: December 12, 2019
    Inventors: Tsung-Yi Huang, Chien-Yu Chen
  • Patent number: 10497806
    Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device and a manufacturing method thereof. The MOS device includes: a semiconductor substrate, a gate, a source, a drain, and two LDDs (Lightly-Doped-Drains). At least one recess is formed at an upper surface of the semiconductor substrate. The recess has a depth which is deeper than the depth of the two LDDs. The recess is filled with a conductive material. A vertical connection portion is formed at a boundary of the recess in the vertical direction, to at least connect one of the LDDs to the drain. The LDD closer to the drain is not laterally in contact with the drain but is connected to the drain by the vertical direction.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 3, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Publication number: 20190348533
    Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes: a semiconductor layer, an isolation oxide region, a first drift oxide region, a second drift oxide region, a well region, a body region, a gate, a source, and a drain. The isolation oxide region, the first drift oxide region, and the second drift oxide region have an isolation thickness, a first thickness, and a second thickness respectively in a vertical direction, wherein the second thickness is less than the first thickness. The second drift oxide region is a chemical vapor deposition (CVD) oxide region, and is formed by a CVD process step. The first drift oxide region is a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure.
    Type: Application
    Filed: March 10, 2019
    Publication date: November 14, 2019
    Inventor: Tsung-Yi Huang
  • Publication number: 20190341491
    Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, a drain and a conductive connection structure. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region in the operation region. The sub-gate is a rectangle shape extending along a width direction, and in parallel with the gate. A conductive connection structure connects the gate and the sub-gate.
    Type: Application
    Filed: December 25, 2018
    Publication date: November 7, 2019
    Inventor: Tsung-Yi Huang
  • Patent number: 10466732
    Abstract: A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: November 5, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chien-Yu Chen, Tsung-Yi Huang, Ting-Wei Liao
  • Publication number: 20190302822
    Abstract: A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.
    Type: Application
    Filed: February 12, 2019
    Publication date: October 3, 2019
    Inventors: Chien-Yu Chen, Tsung-Yi Huang, Ting-Wei Liao
  • Patent number: 10418482
    Abstract: A high voltage device is formed in a semiconductor substrate, and includes: a first deep well, a lateral lightly doped region, a high voltage well, an isolation region, a body region, a gate, a source, a drain, and a first isolation well. The first deep well and the first isolation well are for electrical isolating the high voltage device from neighboring devices below a top surface of the semiconductor substrate. The lateral lightly doped region is located between the first deep well and the high voltage well in a vertical direction, and the lateral lightly doped region contacts the first deep well and the high voltage well. The lateral lightly doped region is for reducing an inner capacitance of the high voltage device when the high voltage device operates, to improve transient response.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 17, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang