Patents by Inventor Tsung-Yi Huang

Tsung-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High Electron Mobility Transistor and Manufacturing Method Thereof
    Publication number: 20140159048
    Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.
    Type: Application
    Filed: May 20, 2013
    Publication date: June 12, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Fang Huang, Po-Chin Peng, Tsung-Chieh Hsiao, Ya-Hsien Liu, K.C. Chang, Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang, Tsung-Yu Yang, Ting-Fu Chang
  • SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF
    Publication number: 20140159111
    Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
    Type: Application
    Filed: October 8, 2013
    Publication date: June 12, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang
  • Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof
    Publication number: 20140151799
    Abstract: The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.
    Type: Application
    Filed: February 5, 2014
    Publication date: June 5, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • HYBRID HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20140151796
    Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
    Type: Application
    Filed: February 10, 2014
    Publication date: June 5, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Double diffused metal oxide semiconductor device and manufacturing method thereof
    Patent number: 8729630
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: May 20, 2014
    Assignee: Richtek Tehnology Corporation, R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • Double diffused metal oxide semiconductor device and manufacturing method thereof
    Patent number: 8728895
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: May 20, 2014
    Assignee: Richtek Corporation Technology R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20140120676
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Application
    Filed: January 2, 2014
    Publication date: May 1, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20140117443
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Application
    Filed: January 2, 2014
    Publication date: May 1, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20140120679
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Application
    Filed: January 2, 2014
    Publication date: May 1, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • Double diffused metal oxide semiconductor device and manufacturing method thereof
    Patent number: 8709900
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: April 29, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • Semiconductor overlapped PN structure and manufacturing method thereof
    Patent number: 8710633
    Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: April 29, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Chien-Hao Huang, Ying-Shiou Lin
  • High electron mobility transistor and manufacturing method thereof
    Patent number: 8710551
    Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: April 29, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Chih-Fang Huang, Chien-Wei Chiu, Ting-Fu Chang, Tsung-Yu Yang, Tsung-Yi Huang
  • Double diffused metal oxide semiconductor device and manufacturing method thereof
    Patent number: 8686500
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device is formed in a first conductive type substrate, and includes a second conductive type high voltage well, a field oxide region, a gate, a second conductive type source, a second conductive type drain, a first conductive type body region, and a first conductive type deep well. The deep well is formed beneath and adjacent to the high voltage well in a vertical direction. The deep well and the high voltage well are defined by a same lithography process step.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 1, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Ching-Yao Yang
  • Hybrid high voltage device and manufacturing method thereof
    Patent number: 8685824
    Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 1, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Double diffused drain metal oxide semiconductor device and manufacturing method thereof
    Patent number: 8686504
    Abstract: The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: April 1, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • High Electron Mobility Transistor and Manufacturing Method Thereof
    Publication number: 20140061724
    Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Inventors: Chih-Fang Huang, Chien-Wei Chiu, Ting-Fu Chang, Tsung-Yu Yang, Tsung-Yi Huang
  • Double Diffused Metal Oxide Semiconductor Device and Manufacturing Method Thereof
    Publication number: 20140061786
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes a first conductive type substrate, a second conductive type high voltage well, a first conductive type deep buried region, a field oxide region, a first conductive type body region, a gate, a second conductive type source, and a second conductive type drain. The deep buried region is formed below the high voltage well with a gap in between, and the gap is not less than a predetermined distance.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu
  • High Electron Mobility Transistor and Manufacturing Method Thereof
    Publication number: 20140061658
    Abstract: The present invention discloses an enhanced mode high electron mobility transistor (HEMT) which includes: a P-type gallium nitride (GaN) layer; a barrier layer, which is formed on and connected to the GaN layer; a dielectric layer, which is formed on and connected to the GaN layer, wherein the barrier layer does not overlap at least part of the dielectric layer; a gate, which is formed on the dielectric layer for receiving a gate voltage; and a source and a drain, which are formed at two sides of the gate on the GaN layer respectively; wherein a two dimensional electron gas (2DEG) is formed at a junction of the GaN layer and the barrier layer which does not include a portion of the junction below the gate, and the 2DEG does not electrically connect the source to the drain when there is no voltage applied to the gate.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Inventors: Chien-Wei Chiu, Tsung-Yi Huang
  • SCHOTTKY BARRIER DIODE AND MANUFACTURING METHOD THEREOF
    Publication number: 20140048815
    Abstract: A Schottky barrier diode (SBD) is disclosed, which includes: a gallium nitride (GaN) layer, formed on a substrate; an aluminum gallium nitride (AlGaN), formed on the GaN layer; an insulation layer, formed on the AlGaN layer; an anode conducive layer, formed on the insulation layer, wherein Schottky contact is formed between a part of the anode conductive layer and the AlGaN layer or between a part of the anode conductive layer and the GaN layer, and another part of the anode conductive layer is separated from the AlGaN layer by the insulation layer; and a cathode conductive layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the cathode conductive layer and the GaN layer or between the cathode conductive layer and the AlGaN layer, and wherein the anode conductive layer is not directly connected to the cathode conductive layer.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu, Chih-Fang Huang, Tsung-Yu Yang
  • Double diffused metal oxide semiconductor device and manufacturing method thereof
    Patent number: 8653594
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: February 18, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su