Patents by Inventor Tsung-Yi Huang

Tsung-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • JUNCTION BARRIER SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150021615
    Abstract: The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.
    Type: Application
    Filed: September 28, 2013
    Publication date: January 22, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Fang Huang, Tsung-Yi Huang, Chien-Wei Chiu, Tsung-Yu Yang, Ting-Fu Chang, Tsung-Chieh Hsiao, Ya-Hsien Liu, Po-Chin Peng
  • TRANSIENT VOLTAGE SUPPRESSOR CIRCUIT, AND DIODE DEVICE THEREFOR AND MANUFACTURING METHOD THEREOF
    Publication number: 20140377940
    Abstract: The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Jin-Lian Su
  • Double diffused drain metal oxide semiconductor device and manufacturing method thereof
    Patent number: 8912601
    Abstract: The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: December 16, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Isolated device and manufacturing method thereof
    Patent number: 8907432
    Abstract: An isolated device is formed in a substrate in which is formed a high voltage device. The isolated device includes: an isolated well formed in the substrate by a lithography process and an ion implantation process used in forming the high voltage device; a gate formed on the substrate; a source and a drain, which are located in the isolated well at both sides of the gate respectively; a drift-drain region formed beneath the substrate surface, wherein the gate and the drain are separated by the drift-drain region, and the drain is in the drift-drain region; and a mitigation region, which is formed in the substrate and has a shallowest portion located at least below 90% of a depth of the drift-drain region as measured from the substrate surface, wherein the mitigation region and the drift-drain region are defined by a same lithography process.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: December 9, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu
  • MANUFACTURING METHOD OF JUNCTION FIELD EFFECT TRANSISTOR
    Publication number: 20140315358
    Abstract: The present invention discloses a manufacturing method of a junction field effect transistor (JFET). The manufacturing method includes: providing a substrate with a first conductive type, forming a channel region with a second conductive type, forming a field region with the first conductive type, forming a gate with the first conductive type, forming a source with the second conductive type, forming a drain with the second conductive type, and forming a lightly doped region with the second conductive type. The channel region is formed by an ion implantation process step, wherein the lightly doped region is formed by masking a predetermined region from accelerated ions of the ion implantation process step, and diffusing impurities with the second conductive type nearby the predetermined region into it with a thermal process step.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 23, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • High voltage device and manufacturing method thereof
    Patent number: 8859373
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a substrate. The high voltage device includes: a gate, a source and drain, a drift region, and a mitigation region. The gate is formed on an upper surface of the substrate. The source and drain are located at both sides of the gate below the upper surface respectively, and the source and drain are separated by the gate. The drift region is located at least between the gate and the drain. The mitigation region is formed below the drift region, and the drift region has an edge closer to the source. A vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: October 14, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu
  • Transient voltage suppressor circuit, and diode device therefor and manufacturing method thereof
    Patent number: 8860082
    Abstract: The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.
    Type: Grant
    Filed: July 15, 2012
    Date of Patent: October 14, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Jin-Lian Su
  • High voltage device and manufacturing method thereof
    Patent number: 8859375
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: October 14, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • LDMOS device having increased punch-through voltage and method for making same
    Patent number: 8841723
    Abstract: The present invention discloses an LDMOS device having an increased punch-through voltage and a method for making same. The LDMOS device includes: a substrate; a well of a first conductive type formed in the substrate; an isolation region formed in the substrate; a body region of a second conductive type in the well; a source in the body region; a drain in the well; a gate structure on the substrate; and a first conductive type dopant region beneath the body region, for increasing a punch-through voltage.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: September 23, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Huan-Ping Chu, Ching-Yao Yang, Hung-Der Su
  • High voltage device and manufacturing method thereof
    Patent number: 8835258
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: September 16, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Huan-Ping Chu
  • Trench Schottky barrier diode and manufacturing method thereof
    Patent number: 8772900
    Abstract: The present invention discloses a trench Schottky barrier diode (SBD) and a manufacturing method thereof. The trench SBD includes: an epitaxial layer, formed on a substrate; multiple mesas, defined by multiple trenches; a field plate, formed on the epitaxial layer and filled in the multiple trenches, wherein a Schottky contact is formed between the field plate and top surfaces of the mesas; a termination region, formed outside the multiple mesas and electrically connected to the field plate; a field isolation layer, formed on the upper surface and located outside the termination region; and at least one mitigation electrode, formed below the upper surface outside the termination region, and is electrically connected to the field plate through the field isolation layer, wherein the mitigation electrode and the termination region are separated by part of a dielectric layer and part of the epitaxial layer.
    Type: Grant
    Filed: July 8, 2012
    Date of Patent: July 8, 2014
    Assignee: Richteck Technology Corporation
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • High Electron Mobility Transistor and Manufacturing Method Thereof
    Publication number: 20140187003
    Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.
    Type: Application
    Filed: March 9, 2014
    Publication date: July 3, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION, R.O.C
    Inventors: Chih-Fang Huang, Chien-Wei Chiu, Ting-Fu Chang, Tsung-Yu Yang, Tsung-Yi Huang
  • MANUFACTURING METHOD OF LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE
    Publication number: 20140179079
    Abstract: The present invention discloses a manufacturing method of a lateral double diffused metal oxide semiconductor (LDMOS) device. The LDMOS device includes: a substrate, an epitaxial layer, a first conductivity type channel stop region, a first conductivity type top region, an isolation oxide region, a field oxide region, a first conductivity type well, a gate, a second conductivity type lightly doped region, a second conductivity type source, and a second conductivity type drain. The present invention defines the channel stop region, the top region, the isolation oxide region, and the field oxide region by a same oxide region mask, wherein the isolation oxide region and the field oxide region are located on the channel stop region and the top region respectively.
    Type: Application
    Filed: October 2, 2013
    Publication date: June 26, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu
  • Double diffused drain metal oxide semiconductor device and manufacturing method thereof
    Patent number: 8759913
    Abstract: The present invention discloses a double diffused drain metal oxide semiconductor (DDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes: a drift region, a gate, a source, a drain, a dielectric layer, and a conductive layer. The drift region includes a first region and a second region. The gate is formed on the substrate, and overlaps the first region from top view. The source and drain are formed at both sides of the gate respectively, and the drain is located in the second region. The drain and the gate are separated by a portion of the second region from top view. The dielectric layer is formed by dielectric material on the gate and the second region. The conductive layer is formed by conductive material on the dielectric layer, and overlaps at least part of the second region from top view.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: June 24, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Ching-Yao Yang, Wen-Yi Liao
  • High voltage device and manufacturing method thereof
    Patent number: 8754476
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a well of a substrate. The high voltage device includes: a field oxide region; a gate, which is formed on a surface of the substrate, and part of the gate is located above the field oxide region; a source and a drain, which are formed at two sides of the gate respectively; and a first low concentration doped region, which is formed beneath the gate and has an impurity concentration which is lower than that of the well surrounded, wherein from top view, the first low concentration doped region has an area within the gate and not larger than an area of the gate, and the first low concentration doped region has a depth which is deeper than that of the source and drain.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: June 17, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventor: Tsung-Yi Huang
  • High Electron Mobility Transistor and Manufacturing Method Thereof
    Publication number: 20140159048
    Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.
    Type: Application
    Filed: May 20, 2013
    Publication date: June 12, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Fang Huang, Po-Chin Peng, Tsung-Chieh Hsiao, Ya-Hsien Liu, K.C. Chang, Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang, Tsung-Yu Yang, Ting-Fu Chang
  • SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF
    Publication number: 20140159111
    Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
    Type: Application
    Filed: October 8, 2013
    Publication date: June 12, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang
  • Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof
    Publication number: 20140151799
    Abstract: The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.
    Type: Application
    Filed: February 5, 2014
    Publication date: June 5, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • HYBRID HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20140151796
    Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
    Type: Application
    Filed: February 10, 2014
    Publication date: June 5, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Double diffused metal oxide semiconductor device and manufacturing method thereof
    Patent number: 8729630
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: May 20, 2014
    Assignee: Richtek Tehnology Corporation, R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su