Patents by Inventor Tsung-Yi Huang

Tsung-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transient voltage suppression device and manufacturing method thereof
    Patent number: 9257421
    Abstract: The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: February 9, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Kuo-Hsuan Lo, Wu-Te Weng
  • Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate
    Patent number: 9252219
    Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: February 2, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Fang Huang, Tsung-Yi Huang, Chien-Wei Chiu, Tsung-Yu Yang, Ting-Fu Chang, Tsung-Chieh Hsiao, Ya-Hsien Liu, Po-Chin Peng
  • Semiconductor device having weak current channel
    Patent number: 9245945
    Abstract: The invention provides a semiconductor device having a weak current channel. The semiconductor device includes a gate, a source and a drain. There are a plurality of insulation layers and a plurality of first conductive type lightly doped regions alternatingly arranged between the gate and the drain; each of the first conductive type lightly doped regions providing a weak current channel between the source and the drain. When the gate is in a relatively low voltage range, the weak current channel is conducted; when the gate is in a relatively high voltage range, the weak current channel is not conducted.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: January 26, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu, Huang-Ping Chu, Chien-Kai Chang
  • Semiconductor composite film with heterojunction and manufacturing method thereof
    Patent number: 9245746
    Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: January 26, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang
  • TRANSIENT VOLTAGE SUPPRESSION DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150364460
    Abstract: The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer.
    Type: Application
    Filed: June 2, 2015
    Publication date: December 17, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Kuo-Hsuan Lo, Wu-Te Weng
  • High voltage device and manufacturing method thereof
    Patent number: 9117901
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 25, 2015
    Assignee: RICHTEK TECHNOLOGY CORPORATION, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Coupling well structure for improving HVMOS performance
    Patent number: 9111957
    Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Liang Chou, Chen-Bau Wu, Weng-Chu Chu, Tsung-Yi Huang, Fu-Jier Fan
  • Semiconductor structure and semiconductor device having the same
    Patent number: 9105491
    Abstract: The invention provides a semiconductor structure and a semiconductor device having such semiconductor structure. The semiconductor structure includes: a substrate; a first well having a first conductivity type, which is provided on the substrate; a second well having a second conductivity type and contacting the first well at a boundary in between in a lateral direction; and a plurality of mitigation regions having the first conductivity type or the second conductivity type, provided in the first well and being close to the boundary in a lateral direction and penetrating the first well in a vertical direction.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: August 11, 2015
    Assignee: Richtek Technology Corporation
    Inventor: Tsung-Yi Huang
  • Junction barrier Schottky diode and manufacturing method thereof
    Patent number: 9105757
    Abstract: The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.
    Type: Grant
    Filed: September 28, 2013
    Date of Patent: August 11, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Chih-Fang Huang, Tsung-Yi Huang, Chien-Wei Chiu, Tsung-Yu Yang, Ting-Fu Chang, Tsung-Chieh Hsiao, Ya-Hsien Liu, Po-Chin Peng
  • High voltage device and manufacturing method thereof
    Patent number: 9105656
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; agate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: August 11, 2015
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Kuo-Hsuan Lo
  • Silicon controlled rectifier for providing electrostatic discharge protection for high voltage integrated circuits
    Patent number: 9093463
    Abstract: A silicon controlled rectifier includes: a substrate; a N well and a P well positioned on a side of the substrate and contact with each other; a first N region and a first P region positioned on an upper surface of the N well and contact with each other; a second N region and a second P region positioned on an upper surface of the P well and contact with each other; a first oxide isolation region isolating the first P region and the second N region; a second oxide isolation region isolating the second N region and the second P region; an anode terminal coupled with the first N region and the first P region; and a cathode terminal coupled with the second N region and the second P region. The first P region has a doping concentration less than 80% of that of the second P region.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: July 28, 2015
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chung-Yu Hung, Jian-Hsing Lee, Tzu-Cheng Kao, Tsung-Yi Huang
  • LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150137232
    Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.
    Type: Application
    Filed: October 9, 2014
    Publication date: May 21, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Ching-Yao Yang, Wen-Yi Liao, Hung-Der Su, Kuo-Cheng Chang
  • OHMIC CONTACT STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME
    Publication number: 20150130067
    Abstract: This invention provides an ohmic contact structure including: a semiconductor substrate having a top surface which includes a plurality of micro-structures; and a conductive layer, which is formed on the micro-structures. An ohmic contact is formed by the conductive layer and the semiconductor substrate. The present invention also provides a semiconductor device having the ohmic contact structure.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chien-Wei Chiu, Ting-Wei Liao, Chieh-Hsiung Kuan, Tsung-Yi Huang, Tsung-Yu Yang
  • HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150123198
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.
    Type: Application
    Filed: January 8, 2015
    Publication date: May 7, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Hybrid high voltage device and manufacturing method thereof
    Patent number: 9018703
    Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: April 28, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Transient voltage suppressor circuit, and diode device therefor and manufacturing method thereof
    Patent number: 9018070
    Abstract: The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: April 28, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Jin-Lian Su
  • High voltage device and manufacturing method thereof
    Patent number: 9012989
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 21, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • TRANSIENT VOLTAGE SUPPRESSION DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150097269
    Abstract: The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device includes: a conductive layer; a P-type semiconductor substrate, which is formed on the conductive layer; an N-type buried layer, which is formed on the semiconductor substrate; a P-type lightly doped layer, which is formed on the buried layer; a P-type cap region, which is formed on the lightly doped layer; and an N-type reverse region, which is formed on the cap region, wherein a Zener diode includes the reverse region and the cap region, and an NPN bipolar junction transistor (BJT) includes the reverse region, the cap region, the lightly doped layer and the buried layer.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Wu-Te Weng
  • METAL OXIDE SEMICONDUCTOR (MOS) DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150091087
    Abstract: The present invention discloses a metal oxide semiconductor (MOS) device and a manufacturing method thereof. The MOS device is formed in a substrate with an upper surface and it includes: an isolation region, a well region, a gate, a lightly-doped-source (LDS), a lightly-doped-drain (LDD), a source, and a drain. The isolation region defines an operation region. The gate includes: a dielectric layer, a stack layer, and a spacer layer, wherein the stack layer separates the operation region to a first side and a second side. The LDS with a first conductive type, is formed in the substrate beneath the upper surface, and at least part of the LDS overlaps the stack layer from a top view. The source with a second conductive type overlaps the spacer layer at the first side. The conductive types of the LDS and the source are different to mitigate the threshold voltage roll-off.
    Type: Application
    Filed: August 11, 2014
    Publication date: April 2, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME
    Publication number: 20150091104
    Abstract: The invention provides a semiconductor structure and a semiconductor device having such semiconductor structure. The semiconductor structure includes: a substrate; a first well having a first conductivity type, which is provided on the substrate; a second well having a second conductivity type and contacting the first well at a boundary in between in a lateral direction; and a plurality of mitigation regions having the first conductivity type or the second conductivity type, provided in the first well and being close to the boundary in a lateral direction and penetrating the first well in a vertical direction.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang