Patents by Inventor Tsung-Yu CHIANG

Tsung-Yu CHIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220130678
    Abstract: The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsinhsiang Tseng, Chi-Ruei Yeh, Tsung-Yu Chiang
  • Publication number: 20210280575
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Publication number: 20210280687
    Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 9, 2021
    Inventors: Sheng-Chou Lai, Tsung-Yu Chiang
  • Patent number: 11018131
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Patent number: 11011618
    Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chou Lai, Tsung-Yu Chiang
  • Patent number: 10957653
    Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien, Tzong-Sheng Chang
  • Publication number: 20210066132
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Tsung-Yu CHIANG, Kuan-Hsin CHEN, Hsin-Lung CHAO, Chen CHU-HSUAN
  • Patent number: 10879127
    Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Shuo Ho, Tsung-Yu Chiang, Chia-Ming Chang, Jyun-Ming Lin
  • Patent number: 10840143
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Hsin-Lung Chao, Chen Chu-Hsuan
  • Publication number: 20200357912
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first gate stack and the second gate stack. The method also includes forming a protection element to cover the second gate stack. The method further includes replacing the first gate stack with a metal gate stack after the formation of the protection element.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Wen YANG, Tsung-Yu CHIANG
  • Publication number: 20200335595
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first metal gate structure in a first dielectric layer. The method includes forming a second metal gate structure in the first dielectric layer, and the second metal gate structure includes a second metal electrode over a second gate dielectric layer. The method also includes forming a mask structure covering the first metal gate structure. The method includes etching a portion of the second gate dielectric layer and a portion of the second metal electrode of the second metal gate structure to form a first conductive portion extending above a top surface of the second gate dielectric layer. The method includes forming a metal layer over the first conductive portion, and the metal layer has a recess, and a top portion of the first conductive portion extends into the recess.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Ching HUANG, Tsung-Yu CHIANG
  • Patent number: 10734522
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack over the semiconductor substrate. The first gate stack includes a metal electrode. The semiconductor device structure also includes a second gate stack over the semiconductor substrate, and the second gate stack includes a polysilicon element.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Wen Yang, Tsung-Yu Chiang
  • Patent number: 10707316
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a dielectric layer over the substrate, a first metal gate structure in the dielectric layer and having a first width and a second metal gate structure in the dielectric layer and having a second width. The first metal gate structure includes a first metal electrode, and the second metal gate structure includes a second metal electrode. The second metal electrode includes a first conductive portion having a third width and a second conductive portion over the first conductive portion and having a fourth width. The fourth width is greater than the third width. The semiconductor device structure also includes two first source/drain portions at opposite sides of the first metal gate structure, and two second source/drain portions at opposite sides of the second metal gate structure.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ching Huang, Tsung-Yu Chiang
  • Publication number: 20200144127
    Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 7, 2020
    Inventors: Wei-Shuo HO, Tsung-Yu CHIANG, Chia-Ming CHANG, Jyun-Ming LIN
  • Publication number: 20200043859
    Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Tsung-Yu CHIANG, Chen KUANG-HSIN, Bor-Zen TIEN, Tzong-Sheng CHANG
  • Patent number: 10522412
    Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Shuo Ho, Tsung-Yu Chiang, Chia-Ming Chang, Jyun-Ming Lin
  • Patent number: 10515902
    Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien, Tzong-Sheng Chang
  • Patent number: 10453741
    Abstract: A method of making a semiconductor device includes forming a gate stack that include a gate electrode and a spacer layer extending along a sidewall of the gate electrode; forming a source/drain (S/D) feature that is adjacent to the gate stack; forming a dielectric layer over the gate stack and the S/D feature; forming a contact hole in the dielectric layer to expose the S/D feature, wherein the contact hole includes a first sidewall that is formed by the spacer layer and part of the dielectric layer; doping an upper portion of the first sidewall; and performing an etching process thereby cleaning oxides in the contact hole.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chien Huang, Tsung-Yu Chiang
  • Patent number: 10347766
    Abstract: Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: July 9, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Shuo Ho, Chia-Ming Chang, Tsung-Yu Chiang, Kuang-Hsin Chen, Bor-Zen Tien
  • Publication number: 20190165125
    Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
    Type: Application
    Filed: September 7, 2018
    Publication date: May 30, 2019
    Inventors: Sheng-Chou Lai, Tsung-Yu Chiang