Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate stack. The first gate stack includes a gate dielectric layer, a first work function metal layer and a second work function metal layer directly on the first work function metal layer. The second work function metal layer and the first work function metal layer have the same metal element. The semiconductor device also includes a second gate stack. The second gate stack includes a gate dielectric layer, a barrier layer and a second work function metal layer. The second work function metal layer and the barrier layer do not have the same metal element. A first thickness of the second work function metal layer of the first gate stack is larger than a second thickness of the second work function metal layer of the second gate stack.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.

Abstract: Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.

Abstract: A semiconductor structure includes a substrate including a first active region, a second active region and an isolation disposed between the first active region and the second active region; a plurality of gates disposed over the substrate and including a first gate extended over the first active region, the isolation and the second active region, and a second gate over the first active region and the second active region; and an inter-level dielectric (ILD) disposed over the substrate and surrounding the plurality of gates, wherein the second gate is configured not to conduct current flow and includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.

Abstract: Some embodiments of the present disclosure provide a semiconductor device including a semiconductive substrate, a metal gate including a metallic layer proximal to the semiconductive substrate. A dielectric layer surrounds the metal gate. The dielectric layer includes a first surface facing the semiconductive substrate and a second surface opposite to the first surface. A sidewall spacer surrounds the metallic layer with a greater longitudinal height. The sidewall spacer is disposed between the metallic layer and the dielectric layer. An etch stop layer over the metal gate comprises a surface substantially coplanar with the second surface of the dielectric layer. The etch stop layer has a higher resistance to etchant than the dielectric layer. A portion of the etch stop layer is over the sidewall spacer.

Abstract: An integrated circuit structure is provided including a substrate, a low voltage device and a high voltage device. The low voltage device has a first beeline distance from a first epitaxial structure to an adjacent gate stack; and the high voltage structure has a second beeline distance from a second epitaxial structure to an adjacent gate stack. The second beeline distance of the high voltage device is greater than the first beeline distance of the low voltage device, so that the leakage current in the high voltage device may be decreased under high voltage operation. Further, a method for manufacturing the integrated circuit structure also provides herein.

Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.

Abstract: Methods for forming a semiconductor device are provided. The method includes forming a first fin and a second fin over a substrate and forming a first isolation structures and a second isolation structure adjacent to the substrate. The first fin is partially surrounded by the first isolation structure and a second fin is partially surrounded by the second isolation structure, and the first isolation structure has a dopant concentration higher than that of the second isolation structure.

Abstract: A semiconductor device includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device also includes a first epitaxial fin and a second epitaxial fin over the semiconductor substrate, and the first epitaxial fin and the second epitaxial fin protrude from the isolation structure. The semiconductor device further includes a gate stack over and traversing the first epitaxial fin and the second epitaxial fin. In addition, the semiconductor device includes a recess extending from a top surface of the isolation structure. The recess is between the first epitaxial fin and the second epitaxial fin.

Abstract: Methods and devices for forming a contact over a metal gate for a transistor are provided. The device may comprise an active area, an isolation area surrounding the active area, and a metal gate above the isolation area, wherein the metal gate comprises a conductive layer. The contact comprises a first contact part within the conductive layer, above the isolation area without vertically overlapping the active area, and a second contact part above the first contact part, connected to the first contact part, and substantially vertically contained within the first contact part.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.

Abstract: A dynamic tag generating apparatus and a dynamic tag generating method thereof are provided. The dynamic tag generating apparatus is disposed in a display apparatus, and the display apparatus is connected to a server. The dynamic tag generating apparatus receives tag update information from the server through the display apparatus, and updates a tag content of the display apparatus according to the tag update information. The dynamic tag generating apparatus provides the tag content to a tag analyzing apparatus so that the tag analyzing apparatus analyzes the tag content.

Abstract: A semiconductor device includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device also includes a first epitaxial fin and a second epitaxial fin over the semiconductor substrate, and the first epitaxial fin and the second epitaxial fin protrude from the isolation structure. The semiconductor device further includes a gate stack over and traversing the first epitaxial fin and the second epitaxial fin. In addition, the semiconductor device includes a recess extending from a top surface of the isolation structure. The recess is between the first epitaxial fin and the second epitaxial fin.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and protruding through a top surface thereof. The semiconductor device also includes a second fin partially surrounded by a second isolation structure and protruding through a top surface thereof. The top surface of the first isolation structure is higher than the top surface of the second isolation structure such that the second fin has a height higher than that of the first fin. The second isolation structure has a dopant concentration higher than that of the first isolation structure.

Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.

Abstract: A system and method of designing a layout for a plurality of different logic operation (LOP) cell technologies includes defining a priority for each LOP cell technology in the plurality of different LOP technologies and forming a layout of the plurality of different LOP cells for formation on a substrate with at least some of the LOP cells of higher priority LOP technologies overlapping LOP cells of lower priority LOP technologies. The system can include a processor coupled to memory where stored code defines the priority for each different cell technology in the plurality of LOP cells and (when the code is executed) the processor forms the layout of a plurality of different LOP cells. All of the LOP cells of higher priority LOP technologies overlap LOP cells of lower priority. The system or method also avoids the overlap of higher priority LOP cells by lower priority LOP cells.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.

Abstract: Methods of modifying a self-aligned contact process in a semiconductor fabrication and a semiconductor device are provided. A method includes forming a transistor over a substrate, including depositing a high-k dielectric layer over the substrate; depositing a work function metal layer over the high-k dielectric layer; forming a metal gate over the work function metal layer; forming two spacers sandwiching the work function metal layer and the metal gate; and forming a doped region in the substrate; etching the work function metal layer and the metal gate to leave a metal residue over inner walls of the two spacers exposing the work function metal layer and the metal gate; modifying the metal residue and the exposed work function metal layer and metal gate to form a metal compound; depositing an insulator covering the metal compound; and forming contact pads respectively electrically connected to the metal gate and the doped region.

Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate stack. The first gate stack includes a gate dielectric layer, a first work function metal layer and a second work function metal layer directly on the first work function metal layer. The second work function metal layer and the first work function metal layer have the same metal element. The semiconductor device also includes a second gate stack. The second gate stack includes a gate dielectric layer, a barrier layer and a second work function metal layer. The second work function metal layer and the barrier layer do not have the same metal element. A first thickness of the second work function metal layer of the first gate stack is larger than a second thickness of the second work function metal layer of the second gate stack.