Patents by Inventor Tsung-Yu CHIANG
Tsung-Yu CHIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180174914Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.Type: ApplicationFiled: February 9, 2018Publication date: June 21, 2018Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Hsin-Lung Chao, Chen Chu-Hsuan
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Publication number: 20180166548Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a dielectric layer over the substrate, a first metal gate structure in the dielectric layer and having a first width and a second metal gate structure in the dielectric layer and having a second width. The first metal gate structure includes a first metal electrode, and the second metal gate structure includes a second metal electrode. The second metal electrode includes a first conductive portion having a third width and a second conductive portion over the first conductive portion and having a fourth width. The fourth width is greater than the third width. The semiconductor device structure also includes two first source/drain portions at opposite sides of the first metal gate structure, and two second source/drain portions at opposite sides of the second metal gate structure.Type: ApplicationFiled: February 10, 2017Publication date: June 14, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Ching HUANG, Tsung-Yu CHIANG
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Publication number: 20180166329Abstract: A method of making a semiconductor device includes forming a gate stack that include a gate electrode and a spacer layer extending along a sidewall of the gate electrode; forming a source/drain (S/D) feature that is adjacent to the gate stack; forming a dielectric layer over the gate stack and the S/D feature; forming a contact hole in the dielectric layer to expose the S/D feature, wherein the contact hole includes a first sidewall that is formed by the spacer layer and part of the dielectric layer; doping an upper portion of the first sidewall; and performing an etching process thereby cleaning oxides in the contact hole.Type: ApplicationFiled: April 12, 2017Publication date: June 14, 2018Inventors: Cheng-Chien HUANG, Tsung-Yu CHIANG
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Publication number: 20180138129Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.Type: ApplicationFiled: January 15, 2018Publication date: May 17, 2018Inventors: Tsung-Yu CHIANG, Chen KUANG-HSIN, Bor-Zen TIEN, Tzong-Sheng CHANG
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Patent number: 9947766Abstract: A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The source/drain region is in the substrate. The etch stop layer is over the source/drain region. The oxide layer is over the etch stop layer. The interlayer dielectric layer is over the oxide layer. The contact plug is electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer.Type: GrantFiled: July 10, 2017Date of Patent: April 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen
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Publication number: 20180102278Abstract: A semiconductor device is provided. The semiconductor device includes a doped isolation structure formed above a substrate, and the doped isolation structure includes a first doped portion and a second doped portion, and a doped concentration of the second doped portion is different from a doped concentration of the first doped portion. The semiconductor device also includes a first fin partially embedded in the doped isolation structure, and a sidewall surface of the first fin is in direct contact with the first doped portion. The semiconductor device includes a second fin partially embedded in the doped isolation structure, and the doped isolation structure is between the first fin and the second fin, and a sidewall surface of the second fin is in direct contact with the second doped portion.Type: ApplicationFiled: December 11, 2017Publication date: April 12, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu CHIANG, Chung-Wei LIN, Kuang-Hsin CHEN, Bor-Zen TIEN
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Patent number: 9941386Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first fin structure and a second fin structure over the substrate. There is a gap between the first fin structure and the second fin structure. The semiconductor device structure includes an isolation structure having a thin portion and a thick portion. A first upper portion of the first fin structure and a second upper portion of the second fin structure protrude from the thin portion. The thick portion is partially between the first upper portion and the second upper portion. The semiconductor device structure includes a dummy gate electrode over the thick portion, the first upper portion, and the second upper portion. The semiconductor device structure includes a gate electrode over the first fin structure and the thin portion.Type: GrantFiled: June 1, 2016Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Wei Lin, Tsung-Yu Chiang
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Patent number: 9911658Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.Type: GrantFiled: December 5, 2016Date of Patent: March 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Hsin-Lung Chao, Chen Chu-Hsuan
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Patent number: 9899265Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.Type: GrantFiled: December 19, 2016Date of Patent: February 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Shuo Ho, Tsung-Yu Chiang, Chia-Ming Chang, Jyun-Ming Lin
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Patent number: 9899382Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and an isolation structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure. The first gate structure has a first top width in a direction that is parallel to the fin structure, the second gate structure has a second top width in a direction that is parallel to the fin structure, and the first top width is greater than the second top width.Type: GrantFiled: June 1, 2016Date of Patent: February 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Ching Huang, Tsung-Yu Chiang, Ya-Wen Yang
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Patent number: 9870998Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.Type: GrantFiled: October 23, 2015Date of Patent: January 16, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien, Tzong-Sheng Chang
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Publication number: 20170365705Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack over the semiconductor substrate. The first gate stack includes a metal electrode. The semiconductor device structure also includes a second gate stack over the semiconductor substrate, and the second gate stack includes a polysilicon element.Type: ApplicationFiled: June 15, 2016Publication date: December 21, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ya-Wen YANG, Tsung-Yu CHIANG
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Patent number: 9842761Abstract: A semiconductor device is provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and a second fin partially surrounded by a second isolation structure. The second isolation structure has a dopant concentration higher than that of the first isolation structure, and a height difference is between a top surface of the first isolation structure and a top surface of the second isolation structure.Type: GrantFiled: January 27, 2017Date of Patent: December 12, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Yu Chiang, Chung-Wei Lin, Kuang-Hsin Chen, Bor-Zen Tien
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Publication number: 20170352740Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first fin structure and a second fin structure over the substrate. There is a gap between the first fin structure and the second fin structure. The semiconductor device structure includes an isolation structure having a thin portion and a thick portion. A first upper portion of the first fin structure and a second upper portion of the second fin structure protrude from the thin portion. The thick portion is partially between the first upper portion and the second upper portion. The semiconductor device structure includes a dummy gate electrode over the thick portion, the first upper portion, and the second upper portion. The semiconductor device structure includes a gate electrode over the first fin structure and the thin portion.Type: ApplicationFiled: June 1, 2016Publication date: December 7, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Wei LIN, Tsung-Yu CHIANG
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Publication number: 20170352656Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and an isolation structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure. The first gate structure has a first top width in a direction that is parallel to the fin structure, the second gate structure has a second top width in a direction that is parallel to the fin structure, and the first top width is greater than the second top width.Type: ApplicationFiled: June 1, 2016Publication date: December 7, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Ching HUANG, Tsung-Yu CHIANG, Ya-Wen YANG
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Publication number: 20170309726Abstract: A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The source/drain region is in the substrate. The etch stop layer is over the source/drain region. The oxide layer is over the etch stop layer. The interlayer dielectric layer is over the oxide layer. The contact plug is electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer.Type: ApplicationFiled: July 10, 2017Publication date: October 26, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu CHIANG, Kuang-Hsin CHEN
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Patent number: 9768069Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with an insulating layer formed thereon. The method includes forming a gate dielectric layer in the first opening and the second opening. The method includes forming a film over the gate dielectric layer. The method includes forming a first work function metal layer in the first opening. The method includes depositing a second work function metal layer in the first opening and the second opening and in direct contact with the first work function metal layer in the first opening and the film in the second opening. A first deposition rate of the second work function metal layer over the first work function metal layer is greater than a second deposition rate of the second work function metal layer over the film.Type: GrantFiled: March 15, 2016Date of Patent: September 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Shuo Ho, Tsung-Yu Chiang, Chia-Chun Liao, Kuang-Hsin Chen
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Patent number: 9711611Abstract: A semiconductor device includes a transistor and a contact pad over a substrate. The transistor includes a high-k dielectric layer, a work function metal layer, a metal gate, two spacers, a metal compound, an insulator and a doped region. The high-k dielectric layer is over the substrate. The work function metal layer is over the high-k dielectric layer. The metal gate is over the work function metal layer. The two spacers sandwich the work function metal layer and the metal gate. The metal compound is over inner walls of the two spacers and over the top surface of the work function metal layer and the metal gate. The insulator covers the metal compound. The doped region is in the substrate. The contact pad is electrically connected to the metal gate.Type: GrantFiled: March 29, 2016Date of Patent: July 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Chiang, Wei-Shuo Ho, Kuang-Hsin Chen
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Patent number: 9711408Abstract: A method of manufacturing an integrated circuit structure includes forming a plurality of gate stacks on a first area and a second area of a substrate. A photo-resist layer is formed over the gate stacks on the first area. An ion-doped layer is formed in the second area. The photo-resist layer is removed. A first etching recess is formed in the first area and between two gate stacks. A second etching recess is formed in the second area and between two gate stacks. An epitaxial material is filled into the first etching recess and the second etching recess to form a first epitaxial structure and a second epitaxial structure.Type: GrantFiled: January 13, 2016Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen
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Patent number: 9704970Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.Type: GrantFiled: May 26, 2016Date of Patent: July 11, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen