Patents by Inventor Tsung Yu

Tsung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11011618
    Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chou Lai, Tsung-Yu Chiang
  • Patent number: 11004771
    Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Chi-Hsi Wu, Shin-Puu Jeng, Tsung-Yu Chen, Wensen Hung
  • Publication number: 20210136099
    Abstract: An abnormal traffic detection method is provided according to an embodiment of the disclosure. The method includes: obtaining network traffic data of a target device; sampling the network traffic data by a sampling window with a time length to obtain sampling data; generating, according to the sampling data, an image which presents a traffic feature of the network traffic data corresponding to the time length; and analyzing the image to generate evaluation information corresponding to an abnormal traffic. In addition, an abnormal traffic detection device is also provided according to an embodiment of the disclosure to improve a detection ability and/or an analysis ability for the abnormal traffic and/or a malware.
    Type: Application
    Filed: September 8, 2020
    Publication date: May 6, 2021
    Applicant: Acer Cyber Security Incorporated
    Inventors: Ming-Kung Sun, Tsung-Yu Ho, Zong-Cyuan Jhang, Chiung-Ying Huang
  • Publication number: 20210121438
    Abstract: Described herein are pharmaceutical compositions and methods for treating and preventing conformational diseases such as, TDP-43 proteinopathies, SMA, amyloid positive cancer, normal and premature aging. Also disclosed are in vitro screening methods for screening a therapeutic candidate to treat conformation diseases, by measuring the expression level of prion-like folding of aggregation-prone proteins or a P53 aggregate.
    Type: Application
    Filed: June 28, 2019
    Publication date: April 29, 2021
    Inventors: Hsiang-Yu CHANG, I-Fan WANG, Tsung-Yu TSAI
  • Publication number: 20210118772
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Josh LIN, Chung-Jen HUANG, Yun-Chi WU, Tsung-Yu YANG
  • Publication number: 20210114900
    Abstract: A method of sterilizing ballast water contains providing a device in a pressurized cabin of a ship, the device includes: a first sterilization unit, multiple second sterilization units, and a third sterilization unit. The first sterilizer includes a first valve connected with a first pump via at least one first pipe, and the multiple second sterilization units are soaked in ballast water of the pressurized cabin. A method of sterilizing the ballast water contains steps of: S1. feeding seawater into the first valve from an exterior of the ship and pumping the seawater into the first sterilizer via the at least one first pipe; S2. magnetizing, wherein the first sterilizer has multiple magnetization elements so as to destroy cell walls of microorganism and bacteria in the seawater by using a magnetic field of the multiple magnetization elements; and S3. inhibiting a growth of the microorganism and the bacteria.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventor: TSUNG-YU CHEN
  • Patent number: 10985125
    Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shu-Chia Hsu, Leu-Jen Chen, Yi-Wei Liu, Shang-Yun Hou, Jui-Hsieh Lai, Tsung-Yu Chen, Chien-Yuan Huang, Yu-Wei Chen
  • Publication number: 20210111182
    Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Patent number: 10978373
    Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chang Ku, Hung-Chi Li, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Publication number: 20210100290
    Abstract: In one embodiment of the present disclosure, the simulator apparatus a disposable, replaceable filter cartridge insertable into a recessed cavity of the main tubing in the interior chamber of a distal end of the cylindrical body, wherein the disposable cartridge comprises a base, spinach, ginger, cranberry extracts, carrot, pomegranate, citrus extract, broccoli, wheat germ and kale; and, a removably attachable coupling securing the filter cartridge in place at the distal end of the cylindrical body to lock the filter cartridge into the recessed cavity of the main tubing. In one embodiment, the apparatus further comprises a removably attachable cover, wherein the cover comprises a grid. In another embodiment the removably attachable cover comprises a screen.
    Type: Application
    Filed: March 19, 2018
    Publication date: April 8, 2021
    Inventors: Tsung-Yu Pan, Frank Winterroth, Chun Liu
  • Publication number: 20210098499
    Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu HUNG, Pei-Wei LEE, Pang-Yen TSAI
  • Patent number: 10962025
    Abstract: A frame structure includes a frame body and at least one vibration absorbing structure. The vibration absorbing structure has a support column and at least one cantilever. The cantilever has a cantilever body, a first end portion and a second end portion. One end of the support column is connected to a wall surface of the frame body. The first end portion of the cantilever is connected to the support column. The cantilever body and the second end portion extend outwardly and swing freely on the wall surface of the frame body. When the cantilever body and the second end portion are swinging, they are not in contact with any peripheral member and the frame structure.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: March 30, 2021
    Assignee: Delta Electronics, Inc.
    Inventors: Kun-Hung Chen, Pao-Hung Tung, Tsung-Yu Lei
  • Patent number: 10957653
    Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien, Tzong-Sheng Chang
  • Publication number: 20210077811
    Abstract: A wearable laser pain relief device contains: a power supply unit, a start unit, a sensing unit, and a drive unit. The power supply unit includes at least one battery and a charging device. The start unit is configured to be pressed by a user to turn on/off and to wake up the wearable laser pain relief device. The sensing unit includes an infrared transmitter and an infrared sensor, and the sensing unit is electrically connected with the start unit. The drive unit is electrically connected with the sensing unit and is configured to receive command signal(s) from the start unit so as to transmit the infrared ray to user's muscle, nerve, and tendon from the sensing unit by ways of a laser head of the drive unit.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 18, 2021
    Inventors: Sung-Ho Wong, Tsung-Yu Chen
  • Publication number: 20210082773
    Abstract: A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Wei Lee, Tsung-Yu Hung, Pang-Yen Tsai, Yasutoshi Okuno
  • Publication number: 20210078956
    Abstract: The present invention provides improved processes for the preparation of elagolix and intermediates thereof. The intermediate of formula VII is achieved by a coupling reaction of a compound of formula V and a N-benzylidene protected compound of formula IV: The present invention is suitable for a large-scale production, avoiding the use of potential genotoxic substances and can be performed under mild conditions.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 18, 2021
    Inventors: Yung-Hung Chang, Tsung-Yu Hsiao, Yuan-Xiu Liao, Hsin-Chang Tseng
  • Publication number: 20210066132
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Tsung-Yu CHIANG, Kuan-Hsin CHEN, Hsin-Lung CHAO, Chen CHU-HSUAN
  • Publication number: 20210066456
    Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Yun-Chi WU, Tsung-Yu Yang, Cheng-Bo Shu, Chien Hung Liu
  • Publication number: 20210043454
    Abstract: A semiconductor device includes a substrate and a semiconductor layer. The substrate includes a planar portion and a plurality of pillars on a periphery of the planar portion. The pillars are shaped as rectangular columns, and corners of two of the pillars at the same side of the planar portion are aligned in a horizontal direction or a direction perpendicular to the horizontal direction. The semiconductor layer is disposed over the planar portion and between the pillars.
    Type: Application
    Filed: October 13, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Wei Lee, Pang-Yen Tsai, Tsung-Yu Hung
  • Patent number: D912471
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 9, 2021
    Inventor: Tsung-Yu Tsai