Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

Abstract: A package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor includes a substrate, a block bonded on the substrate, a first die bonded on the block, a second die disposed over the first die, and a heat spreader covering the block and having a surface facing toward and proximal to the block. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the block.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

Abstract: The present invention discloses a method for rapidly estimating for a remaining capacity of a battery, comprising performing a constant current charge to the battery in a first period, instantly capturing a voltage/temperature of the battery in a frequency, and generating a voltage-time graph; after leaving the battery along for a second period, instantly capturing the voltage/temperature of the battery in the frequency; calculating a voltage rising rate during the first period; calculating a voltage drop rate during a leaving-along period; calculating a critical sample time; applying the critical sample time, and comparing the voltage-time graph measured in the first period, to obtain a critical sampling voltage; calculating a voltage difference slope; calculating a charging time, which is consumed by charging the battery from a lower-bound voltage to an upper-bound voltage with the constant current; calculating a compensation ratio value; and calculating the remaining capacity of the battery.

Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

Abstract: The present invention provides improved processes for purifying semaglutide or liraglutide. Semaglutide or liraglutide is purified via two sequential RP-HPLC purifications followed by a salt-exchange step, where a pH is kept constant in the first and second purification steps. In particular, the processes utilize a halogenated solvent in a sample preparation step, which provides better solubility and an environment suitable for decarboxylation for crude semaglutide or liraglutide prior to a RP-HPLC purification.

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A semiconductor device includes a semiconductor substrate and a pair of memory device structures. The semiconductor substrate includes a common source/drain region and a pair of individual source/drain regions, in which the common source/drain region is between the individual source/drain regions. The memory device structures each corresponds to one of the individual source/drain regions. Each memory device structure includes a trap storage structure, a control gate, a cap structure, and a word line. The trap storage structure is between the common source/drain region and the corresponding individual source/drain region. The control gate is over the trap storage structure. The cap structure is over the control gate, in which the cap structure comprises a nitride layer over the control gate and an oxide layer over the nitride layer. The word line is over the semiconductor substrate and laterally spaced from the control gate.

Abstract: A motor comprises a housing having a space, a stator including a spool casing arrayed in the space, a rotor containing an axle and a magnet located inside the spool casing, the axle penetrating the magnet and having two ends protruding out of the housing, wherein the axle has two ends respectively allocated with an end-shield bearing integrating with the spool casing and an bottom-plate bearing detachably mounting on the bottom side of the housing in order to improve the concentricity of the motor.

Abstract: A method for synchronous control of a gantry mechanism with online inertia matching is applicable to a machine tool equipped with a gantry mechanism. The gantry mechanism includes two rails, a crossbeam and a saddle, in which the saddle is disposed on the crossbeam, and the crossbeam is disposed by crossing the two rails. Each of the two rails is furnished with a driving apparatus for synchronously driving the crossbeam, and the driving apparatus includes a drive motor and a lead screw. This method includes the steps of: obtaining gantry-mechanism information; detecting position information of the saddle on the crossbeam; evaluating the position information and the gantry-mechanism information to derive load-inertia variety information; and, evaluating the load-inertia variety information to adjust torque-output information of the drive motor corresponding to the respective driving apparatus.

Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

Abstract: A joint bending state determining device comprises a sensor group and a processor. The sensor group comprises first and second gravity sensors. The first/second gravity sensor generates a first/second polar angle and a first/second azimuth angle. The processor obtains a first length corresponding to the first gravity sensor and a second length corresponding to the second gravity sensor, obtains a set of coordinates of a joint in a coordinate system according to the first polar angle, the first azimuth angle and the first length, obtains a set of coordinates of the second gravity sensor in the coordinate system according to the set of coordinates of the joint, the second polar angle, the second azimuth angle and the second length, and obtains a joint angle according to the set of coordinates of the second gravity sensor in the coordinate system, the first length and the second length.