Patents by Inventor Tsung Yu

Tsung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210384154
    Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Inventors: Kuan-Yu Huang, Li-Chung Kuo, Sung-Hui Huang, Shang-Yun Hou, Tsung-Yu Chen, Chien-Yuan Huang
  • Publication number: 20210374949
    Abstract: The present application related to a method for detecting an object image using a convolutional neural network. Firstly, obtaining feature images by Convolution kernel, and then positioning an image of an object under detected by a default box and a boundary box from the feature image. By Comparing with the sample image, the detected object image is classifying to an esophageal cancer image or a non-esophageal cancer image. Thus, detecting an input image from the image capturing device by the convolutional neural network to judge if the input image is the esophageal cancer image for helping the doctor to interpret the detected object image.
    Type: Application
    Filed: October 27, 2020
    Publication date: December 2, 2021
    Inventors: HSIANG-CHEN WANG, HAO-YI SYU, TSUNG-YU YANG, YU-SHENG CHI
  • Publication number: 20210375769
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.
    Type: Application
    Filed: August 9, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Kai CHENG, Tsung-Shu LIN, Tsung-Yu CHEN, Hsien-Pin HU, Wen-Hsin WEI
  • Patent number: 11189546
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Josh Lin, Chung-Jen Huang, Yun-Chi Wu, Tsung-Yu Yang
  • Publication number: 20210366805
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 25, 2021
    Inventors: CHI-HSI WU, WENSEN HUNG, TSUNG-SHU LIN, SHIH-CHANG KU, TSUNG-YU CHEN, HUNG-CHI LI
  • Publication number: 20210366889
    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Publication number: 20210343619
    Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Publication number: 20210331373
    Abstract: The present disclosure provides a fabric structure including at least one fiber interlaced in a first pattern, and a surface layer having a second pattern not corresponding to the first pattern. The fiber includes a thermoplastic component and a functional component. The surface layer comprises a fused portion of the thermoplastic component and covers the functional component.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 28, 2021
    Inventors: KUO-KUANG CHENG, PAI-HSIANG WU, CHIEN-CHIA HUANG, TSUNG-YU TSAI, CHIEH LEE
  • Publication number: 20210320201
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a word line, a plurality of first impurity regions, a second impurity region, and an isolation film. The word line is W-shaped, is disposed in the substrate, and includes a base and a pair of legs connected to the base. The first impurity regions are disposed in the substrate and on either side of the word line. The second impurity region is disposed between the legs of the word line. The isolation film is disposed in the substrate, wherein the word line is surrounded by the isolation film.
    Type: Application
    Filed: April 10, 2020
    Publication date: October 14, 2021
    Inventor: TSUNG-YU TSAI
  • Patent number: 11142795
    Abstract: Disclosed herein is a novel use of C-type lectin 18 (CLEC18) in disease prognosis. According to embodiments of the present disclosure, the mRNA or protein level of CLEC18 may serve as an indicator for diagnosing hepatitis B virus (HBV) infection, hepatitis B e antigen (HBeAg) loss and seroconversion, and/or liver fibrosis.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: October 12, 2021
    Assignee: ACADEMIA SINICA
    Inventors: Shie-Liang Hsieh, Ya-Lang Huang, Tsung-Yu Tsai
  • Publication number: 20210305899
    Abstract: A power converter is provided. A driver circuit is connected between a controller circuit and a switch circuit. The switch circuit is connected to an inductor. The inductor is connected in series with a first capacitor and grounded through the first capacitor. A first comparison input terminal of a first comparator is connected to an output terminal between the inductor and the first capacitor. A second comparison input terminal of the first comparator is grounded through a second capacitor. The controller circuit outputs a control signal for controlling the driver circuit to drive the switch circuit according to a comparison signal outputted by the first comparator. A reference current source provides a reference current to the second capacitor. A first terminal of a first resistor is connected to the second capacitor. A second terminal of the first resistor is coupled to a reference potential.
    Type: Application
    Filed: June 24, 2020
    Publication date: September 30, 2021
    Inventors: Jen-Chien Hsieh, TSUNG-YU WU
  • Publication number: 20210304924
    Abstract: The present invention provides a structure of resistor element, which comprises a protective layer around electrodes to elongate the path of corrosion when gaseous water or sulfur leaking in. Therefore, the protective layer structure can elongate the life of the resistor element.
    Type: Application
    Filed: July 15, 2020
    Publication date: September 30, 2021
    Inventors: MING-CHIEH KUO, TSUNG-YU TSAI, CHI-YU LU
  • Publication number: 20210299960
    Abstract: A three-dimensional printing apparatus includes a tank, a transparent plate, a printing platform, a projector and a heat dissipation assembly. The tank accommodates a photocurable material, and the transparent plate is disposed adjacent to the tank. The printing platform and the projector are respectively disposed on opposite sides of the transparent plate. The heat dissipation assembly is disposed adjacent to the tank.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Applicant: Young Optics Inc.
    Inventor: Tsung Yu Liu
  • Publication number: 20210292413
    Abstract: Disclosed herein is a novel monoclonal antibody exhibiting binding affinity to Siglec-3 receptor. According to the embodiment, the monoclonal antibody is capable of reversing HBV-induced immunosuppression. Accordingly, also disclosed herein are the uses thereof in the treatment and/or prophylaxis of hepatitis B virus (HBV) infection.
    Type: Application
    Filed: September 25, 2018
    Publication date: September 23, 2021
    Applicant: Academia Sinica
    Inventors: Shie-Liang HSIEH, Tsung-Yu TSAI, An-Suei YANG, Chung-Ming YU, Cheng-Yuan PENG
  • Publication number: 20210280687
    Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 9, 2021
    Inventors: Sheng-Chou Lai, Tsung-Yu Chiang
  • Publication number: 20210280575
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Publication number: 20210280491
    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: Tsung-Shu Lin, Wensen Hung, Hung-Chi Li, Tsung-Yu Chen
  • Publication number: 20210265368
    Abstract: A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 26, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ching-Hua Chen, Bing-Chen Ji, Shun-Tsung Yu, Ming-Yuan Lin, Han-Chao Lai, Jih-Wen Chou, Chen-Chiu Hsue
  • Patent number: D266592
    Type: Grant
    Filed: May 19, 1980
    Date of Patent: October 19, 1982
    Assignee: E. F. Bavis & Associates, Inc.
    Inventor: Edward F. Bavis
  • Patent number: D935775
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 16, 2021
    Inventor: Tsung-Yu Tsai
  • Patent number: D937519
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: November 30, 2021
    Inventors: Tsung-Yu Tsai, Hung-Chih Kuo