Patents by Inventor Tsung Yu

Tsung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10505015
    Abstract: A memory device includes a semiconductor substrate and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a top surface of the control gate is lower than a top surface of the metal gate. The storage layer includes two oxide layers and a nitride layer, and the nitride layer is interposed in between the two oxide layers.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Ru Lin, Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 10504913
    Abstract: A semiconductor device includes a substrate, a trap storage structure, a control gate, a cap structure, a word line well, a source line, spacers, a gap oxide layer, a word line and a gate oxide layer. The trap storage structure includes a first oxide layer, a nitride layer and a second oxide layer stacked on the substrate. The control gate is directly on the trap storage structure. The cap structure is stacked on the control gate to form a stacked structure. The word line well and the source line are disposed in the substrate at opposite sides of the stacked structure. The spacers are on sidewalls of the stacked structure. The gap oxide layer is on a sidewall of one spacer. The word line is on the word line well and the gap oxide layer. The gate oxide layer is between the word line and the word line well.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Yang, Chung-Jen Huang
  • Publication number: 20190372483
    Abstract: A piezoelectric motorization system for driving mechanical loads multi-dimensionally by an electronic circuitry is disclosed. The piezoelectric motorization system has a piezoelectric apparatus that is constructed by a mechanically flexible body that has multiple piezoelectric actuators attached its surfaces, where these actuators are controlled by an electronic circuitry. The mechanically flexible body has a finite structure with a sets of boundary conditions to determine its out-of-plane resonant modes. The electronic circuitry inject at least two sets of control signals into different groups of actuators at or near different resonant frequencies. Using these control signals, traveling waves can be generated on the piezoelectric apparatus to move mechanical loads placed on its surface. Or, the traveling waves are used to propel the piezoelectric apparatus for motorization.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 5, 2019
    Inventors: CHIH-KUNG LEE, YU-HSIANG HSU, WEN-JONG WU, TSUNG-YU CHU, YU-MIN LIN
  • Publication number: 20190367812
    Abstract: A liquid crystal composition includes at least one polar compound represented by Formula (I), at least one polar compound represented by Formula (II), at least one compound represented by Formula (III), at least one compound represented by Formula (IV), and at least one compound represented by Formula (V), in which Formulae (I) to (V) are as defined herein.
    Type: Application
    Filed: February 28, 2019
    Publication date: December 5, 2019
    Applicants: DAILY-XIANHUA OPTOELECTRONICS MATERIALS CO., LTD., Yantai Xianhua Chem-Tech Co., Ltd.
    Inventors: Tsung-Yu Tsai, Shu-Ling Lo, Ziqian Shi, Huan Yin, Fengmei Fang, Xiangbo Dong, Peichuan Feng
  • Patent number: 10483187
    Abstract: In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wensen Hung, Ming-Fa Chen, Tsung-Yu Chen
  • Publication number: 20190347902
    Abstract: A gaining device includes a prize pool switch control system, which includes an activation threshold calculating element and a control computing unit. The activation threshold calculating element generates at least one activation threshold according to a betting selection of a player and a designated computation method. The control computing unit performs a procedure of: a) capturing the at least one activation threshold and a plurality of prize money values of a prize money server device; b) comparing the prize money values with the at least one activation threshold, and generating an activation signal when at least one of the prize money values corresponds to the at least one activation signal; and c) transmitting the activation signal to the prize money server device to cause a prize money award of the prize money value corresponding to the at least one activation threshold to be in a triggerable state.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Inventors: SHUN-TSUNG HSU, TSUNG-YU HSU, CHANG-YI WANG, CHIA-CHING FU
  • Publication number: 20190348386
    Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.
    Type: Application
    Filed: February 15, 2019
    Publication date: November 14, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Yu HUANG, Sung-Hui HUANG, Shu-Chia HSU, Leu-Jen CHEN, Yi-Wei LIU, Shang-Yun HOU, Jui-Hsieh LAI, Tsung-Yu CHEN, Chien-Yuan HUANG, Yu-Wei CHEN
  • Patent number: 10475877
    Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
  • Patent number: 10461014
    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Wensen Hung, Hung-Chi Li, Tsung-Yu Chen
  • Patent number: 10454557
    Abstract: A method for transmitting reference signals includes: determining, by a wireless transmitting device, a first vector set used for calculating a first vector subspace that includes a channel frequency response vector corresponding to a subcarrier; calculating, by the wireless transmitting device, a second vector set including several second vectors derived from performing dot product operations to each vector in the first vector set with a conjugate vector of each vector in the first vector set; calculating, by the wireless transmitting device, a null space of a second vector subspace spanned by the second vector set and determining, by the wireless transmitting device, a cover code from the null space; and transmitting a first reference signal and a second reference signal which is a dot product of the first reference signal and the cover code on the subcarrier from the wireless transmitting device to a wireless receiving device.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 22, 2019
    Assignee: Institute For Information Industry
    Inventors: Tsung-Yu Tsai, Chin-Gwo Ma
  • Patent number: 10453741
    Abstract: A method of making a semiconductor device includes forming a gate stack that include a gate electrode and a spacer layer extending along a sidewall of the gate electrode; forming a source/drain (S/D) feature that is adjacent to the gate stack; forming a dielectric layer over the gate stack and the S/D feature; forming a contact hole in the dielectric layer to expose the S/D feature, wherein the contact hole includes a first sidewall that is formed by the spacer layer and part of the dielectric layer; doping an upper portion of the first sidewall; and performing an etching process thereby cleaning oxides in the contact hole.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chien Huang, Tsung-Yu Chiang
  • Patent number: 10428052
    Abstract: The present disclosure provides efficient, economical, and improved processes for synthesizing lifitegrast and intermediates thereof. The currently discloses processes provide a direct synthetic route, avoiding protection or deprotection steps. The currently disclosed process also provides processes for synthesizing lifitegrast using a reduced number of synthetic steps.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 1, 2019
    Assignee: ScinoPharm Taiwan, Ltd.
    Inventors: Ming-Chih Wu, Tsung-Yu Hsiao
  • Patent number: 10416655
    Abstract: Machining methods for machine tools where a workpiece can be manually moved by an operator or by automatic operation. A drawing file is displayed on a screen and machining is performed. An evaluation is performed to determine if the processed points of the workpiece match the desired processing coordinates within a tolerance range. Accordingly, the system is selectively activated to prevent processing at incorrect processing points or deviating from the tolerance range of the desired processing points. Processing yield rate is improved and all processing points are monitored by the system and displayed on a drawing file screen.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: September 17, 2019
    Inventors: Chiao-Chin Shih, Tsung-Yu Shih
  • Patent number: 10394404
    Abstract: A touch display panel includes a substrate, a first sensing electrode layer. The first sensing electrode layer is disposed on the substrate. The first sensing electrode includes a plurality of first metal conductive lines and a plurality of second metal conductive lines connected with the plurality of first metal conductive lines. The first and second metal conductive lines are respectively arranged along different directions. The outermost one of the plurality of first metal conductive line has a first protruding portion.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 27, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Tsung-Yu Wang, Pei-Chieh Chen, Chao-Hsiang Wang
  • Publication number: 20190252294
    Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Chi-Hsi Wu, Shin-Puu Jeng, Tsung-Yu Chen, Wensen Hung
  • Patent number: 10382878
    Abstract: A sound reproducing method used in sound reproducing apparatus that includes the steps outlined below is provided. A sound signal with a three-dimensional (3D) sound generating process is generated according to listener data and sound data. Whether a sound source position is within a target region relative to a listener position within a virtual environment is determined according to the listener data and the sound data. The sound signal is multiplied by an adjusting function to enhance peaks and valleys of the sound signal while maintaining a behavior of the sound signal when the sound source position is within the target region. The sound signal is reproduced.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: August 13, 2019
    Assignee: HTC Corporation
    Inventors: Yan-Min Kuo, Chun-Min Liao, Li-Yen Lin, Chi-Tang Ho, Tien-Ming Wang, Tsung-Yu Tsai
  • Publication number: 20190241606
    Abstract: A process for preparing cangrelor tetrasodium comprising: a) reacting a compound of formula M1 with morpholine to form a compound of formula M2; and b) reacting the compound of formula M2 with clodronic acid to provide cangrelor tetrasodium
    Type: Application
    Filed: February 5, 2018
    Publication date: August 8, 2019
    Inventors: Tsung-Yu Hsiao, Chen-Wei Lin, Yu-Hui Huang, Meng-Fen Ho, Kuan-Hsun Wang
  • Patent number: D855408
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 6, 2019
    Inventor: Tsung-Yu Tsai
  • Patent number: D856420
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 13, 2019
    Inventor: Tsung-Yu Tsai
  • Patent number: D857094
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 20, 2019
    Inventor: Tsung-Yu Tsai