Abstract: A time and frequency synchronization method that includes the steps outlined below is provided. A wireless signal from a base station is received. The wireless signal is delayed on a time domain and is further correlated with the original wireless signal to generate a delayed and correlated signal. Primary symbols related to a primary synchronization signal are delayed and are further correlated with the original primary symbols to generate delayed and correlated primary symbols. The delayed and correlated signal and the delayed and correlated primary symbols are correlated to identify the position of the primary synchronization signal based on a primary peak value. The position of the secondary synchronization signal is identified based on the position of the primary synchronization signal.

Abstract: Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.

Abstract: A semiconductor device includes a semiconductor substrate and a pair of memory device structures. The semiconductor substrate includes a common source/drain region and a pair of individual source/drain regions, in which the common source/drain region is between the individual source/drain regions. The memory device structures each corresponds to one of the individual source/drain regions. Each memory device structure includes a trap storage structure, a control gate, a cap structure, and a word line. The trap storage structure is between the common source/drain region and the corresponding individual source/drain region. The control gate is over the trap storage structure. The cap structure is over the control gate, in which the cap structure comprises a nitride layer over the control gate and an oxide layer over the nitride layer. The word line is over the semiconductor substrate and laterally spaced from the control gate.

Abstract: Embodiments of the present disclosure provide a method of generating mandrel patterns. A mandrel pattern is generated by constructing a boundary box, initiating a plurality of lead mandrels, and extending the lead mandrels across the boundary box. When a pattern region includes holes, portions of mandrels are removed from the holes after extension of the leading mandrels.

Abstract: A battery health state evaluation method for evaluating a health state of a battery comprises a charging step, an idling step, a pulse discharging step, an evaluation index calculating step, and an evaluation result yielding step. The evaluation index calculating step retrieves a continuous voltage data and a continuous current data in a charging process, an idling process, and a pulse discharge process and calculates a plurality of evaluation indexed according to the continuous voltage data and continuous current data. The evaluation indexes are associated with the health state of the battery. The evaluation result yielding step evaluates the health state of the battery according to the indexes and yields an evaluation result. Therefore, the battery health state evaluation method is easy, convenient, and effective in performing a test quickly and accurately.

Abstract: A functionless transistor device includes a semiconductor substrate, a channel, a first source/drain, a second source/drain, a gate and a gate dielectric layer. The channel includes a first channel extending in a lateral direction, and a second channel extending in a vertical direction. The first source/drain is in contact with the first channel. The second source/drain is in contact with the second channel. The channel, the first source/drain and the second source/drain have the same doping type. The gate is disposed over an upper surface of the first channel and side surfaces of the second channel, and the gate has a second doping type opposite to the first doping type. The gate dielectric layer is disposed between the gate and the channel.

Abstract: A synchronization method, suitable between a first electronic device and a second electronic device, includes following operations. A first pulse of a wireless signal sent from the first electronic device is received by the second electronic device. A first status of the second electronic device is determined. A second pulse of the wireless signal is received after the first pulse. A receiving time gap between the first pulse being received and the second pulse being received by the second electronic device is measured. A new status of the second electronic device is determined according to the receiving time gap and the first status of the second electronic device. Whether to synchronize a system clock on the second electronic device with the second pulse of the wireless signal is determined according to the new status.

Abstract: A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.

Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.

Abstract: A servo tuning device adapted to a multi-axis machine tool at least having two linear axes and a rotation axis used for a moving base and a working platform to move relatively along the two linear axes and the rotation axis. The servo tuning device includes a reflection component, a photoelectric sensor and a processor. The reflection component is configured to be disposed on one of the moving base and the working platform and has a reflection surface. The photoelectric sensor has a light-emitting element and a light-receiving element facing the reflection surface. The photoelectric sensor is configured to be disposed on the other one of the moving base and the working platform. The processor records information of relative movement between the photoelectric sensor and the reflection surface for calculating a loop gain value used for tuning a servo setting of the two linear axes or the rotation axis.

Abstract: A time and frequency synchronization method that includes the steps outlined below is provided. A wireless signal from a base station is received and orthogonal frequency-division multiplexing symbols of a primary synchronization signal of the wireless signal on a time domain is identified. The orthogonal frequency-division multiplexing symbols are transformed to a frequency domain to generate original symbol signals. An inner product of the original symbol signals and the received symbol signals is generated to obtain a product of a power leakage coefficient and a channel gain. A line search is performed to approximate an actual value of a fractional carrier frequency offset of the wireless signal based on the power leakage coefficient.

Abstract: The present disclosure provides a semiconductor structure including a substrate, a first die over the substrate, a second die over the first die, a heat spreader having a sidewall facing toward and proximal to a sidewall of the first die, and a thermal interface material (TIM) between the sidewall of the first die and the sidewall of the heat spreader. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the TIM.

Abstract: A memory device includes a semiconductor substrate having a cell region and a peripheral region surrounding the cell region and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a high-? dielectric film wrapping around the metal gate, and a top surface of the control gate is lower than a top surface of the metal gate.

Abstract: A display device that includes a substrate having a display region and an adjacent peripheral region is provided, including; a plurality of sub-pixels provided within the display region; a plurality of data lines electrically connected to the sub-pixels; and a first electronic circuit group and a second electronic circuit group provided in the peripheral region, connected to the corresponding data lines. The first electronic circuit group includes a plurality of first electronic circuits, and the second electronic circuit group includes a plurality of second electronic circuits. Two adjacent first electronic circuits are arranged with a first interval therebetween, and the first interval has a first width. Two adjacent second electronic circuits are arranged with a second interval therebetween, and the second interval has a second width. The first width and the second width are different.

Abstract: A frame structure includes a frame body and at least one vibration absorbing structure. The vibration absorbing structure has a support column and at least one cantilever. The cantilever has a cantilever body, a first end portion and a second end portion. One end of the support column is connected to a wall surface of the frame body. The first end portion of the cantilever is connected to the support column. The cantilever body and the second end portion extend outwardly and swing freely on the wall surface of the frame body. When the cantilever body and the second end portion are swinging, they are not in contact with any peripheral member and the frame structure.

Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.