Patents by Inventor Tsutomu Fujita

Tsutomu Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7128285
    Abstract: An object of the present invention is to diminish the sizes of most disintegrated material effectively, said sizes being determined by the box seats made on the surface of the under roll (7). In a disintegrator (1) having a case (4) with an upper hopper 2 and under exit (3), a pair of upper rolls (5, 6), an under roll (7) located below the upper rolls, and knives (8,9) projecting from inner surface of the case (4) toward the under roll (7) comprising a number of annular grooves (25) formed on the under roll (7), each groove (25) being coupled by a rotative disk cutter (27) at under side of the knives (8, 9). The under roll (7) is provided with polygonal installation seats (13), between adjoining installation seats (13) each attached by a number of cutting edge blocks (14) on a same circumference, said annular grooves (25) are formed between the adjoining installation seats (13).
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: October 31, 2006
    Assignee: Kabushiki Kaisha Igusundo
    Inventor: Tsutomu Fujita
  • Publication number: 20050210267
    Abstract: An object of the present invention is to provide a user authentication method and system, an information terminal device and a service providing server, a subject identification method and system, a correspondence confirmation method and system, an object confirmation method and system, which are capable of assuring authentication and/or confirmation of a person, an animal and a plant, or an object and improving precision thereof, and program products for them. In order to perform user authentication when a user of an information terminal device 30 such as a cellular phone or the like receives a service from a service providing server 20 via a network, iris authentication is performed, and a password is automatically updated every time a service is provided to generate a new password to be used when a next service is provided, and the new password is stored in both the information terminal device 30 and the service providing server 20.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 22, 2005
    Inventors: Jun Sugano, Tsutomu Fujita, Masatomo Kanegae
  • Publication number: 20040206836
    Abstract: An object of the present invention is to diminish the sizes of most disintegrated material effectively, said sizes being determined by the box seats made on the surface of the under roll (7).
    Type: Application
    Filed: January 21, 2004
    Publication date: October 21, 2004
    Inventor: Tsutomu Fujita
  • Publication number: 20030234867
    Abstract: An information terminal for imaging a first object at a normal distance and a second object nearer than the first object readily with high precision. The information terminal has an imaging lens and an imaging device for capturing an image formed by the imaging lens. The imaging lens is a multifocal lens and composed of a first lens portion having a first focal length for imaging the first object (e.g., the user of the information terminal) at a normal distance and a second lens portion having a second focal length for imaging the second object (e.g., a bar code) nearer than the first object. The first and second lens portions are arranged on the same plane and formed in one piece.
    Type: Application
    Filed: April 2, 2003
    Publication date: December 25, 2003
    Inventors: Tsutomu Fujita, Masatomo Kanegae
  • Publication number: 20030024132
    Abstract: A cargo handling vehicle comprises cargo carriers 21, a lift unit 1, a vehicle main body 24, and a running system 3, and the cargo handling vehicle further comprises a lift height detecting section 2 for detecting the vertical position of the cargo carriers 21, a traveling distance measuring section 4 for measuring a forward distance S1 covered by the vehicle main body 24 which starts its forward movement after the cargo carriers 21 are started to be raised and a rearward distance S2 covered by the vehicle main body 24 which starts its rearward movement after having completed its forward movement, and a movement control section 9 for prohibiting the lowering movement of the cargo carriers 21 until a rearward distance to be covered by the vehicle main body 24 which starts its rearward movement in a state in which the vertical position H2 of the raised cargo carriers 21 exceeds a preset reference height H1 becomes equal to or greater than the forward distance covered by the vehicle main body 24.
    Type: Application
    Filed: June 14, 2001
    Publication date: February 6, 2003
    Applicant: NIPPON YUSOKI CO., LTD.
    Inventors: Kazumasa Kokura, Tsutomu Fujita, Toshihiro Suzuki
  • Patent number: 6313493
    Abstract: The semiconductor device of the invention includes a plurality of circuit blocks including a first circuit block and a second circuit block, a block parameter of the first circuit block being different from a block parameter of the second circuit block. In the semiconductor device, the first circuit block is formed on a first semiconductor chip, and the second circuit block is formed on a second semiconductor chip and is electrically connected with the first circuit block.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: November 6, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiki Mori, Ichiro Nakao, Tsutomu Fujita, Reiji Segawa
  • Patent number: 6226223
    Abstract: In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: May 1, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Shirahama, Tsutomu Fujita, Masashi Agata, Kazunari Takahashi, Naoki Kuroda
  • Patent number: 6181620
    Abstract: The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: January 30, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masashi Agata, Kazunari Takahashi, Tsutomu Fujita, Naoki Kuroda, Toshio Yamada
  • Patent number: 6169684
    Abstract: A cache memory including a first memory array and a main memory including a second memory array are integrated together on the same semiconductor substrate. Each memory cell in the first memory array is of a 2Tr1C type including: first and second transistors, the sources of which are connected together; and a data storage capacitor, one of the two electrodes of which is connected to the common source of the first and second transistors. Each memory cell in the second memory array is of a 1Tr1C type including: a third transistor; and a data storage capacitor, one of the two electrodes of which is connected to the source of the third transistor.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazunari Takahashi, Masashi Agata, Naoki Kuroda, Tsutomu Fujita
  • Patent number: 6064585
    Abstract: The semiconductor device of the invention includes a plurality of circuit blocks including a first circuit block and a second circuit block, a block parameter of the first circuit block being different from a block parameter of the second circuit block. In the semiconductor device, the first circuit block is formed on a first semiconductor chip, and the second circuit block is formed on a second semiconductor chip and is electrically connected with the first circuit block.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: May 16, 2000
    Assignee: Matsushita Electric Industrial Co.
    Inventors: Toshiki Mori, Ichiro Nakao, Tsutomu Fujita, Reiji Segawa
  • Patent number: 6023440
    Abstract: A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: February 8, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisakazu Kotani, Hironori Akamatsu, Tsutomu Fujita
  • Patent number: 5949733
    Abstract: A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: September 7, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisakazu Kotani, Hironori Akamatsu, Tsutomu Fujita
  • Patent number: 5838603
    Abstract: The semiconductor device of the invention includes a plurality of circuit blocks including a first circuit block and a second circuit block, a block parameter of the first circuit block being different from a block parameter of the second circuit block. In the semiconductor device, the first circuit block is formed on a first semiconductor chip, and the second circuit block is formed on a second semiconductor chip and is electrically connected with the first circuit block.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: November 17, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiki Mori, Ichiro Nakao, Tsutomu Fujita, Reiji Segawa
  • Patent number: 5805524
    Abstract: A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.
    Type: Grant
    Filed: January 30, 1996
    Date of Patent: September 8, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisakazu Kotani, Hironori Akamatsu, Tsutomu Fujita
  • Patent number: 5661066
    Abstract: In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p.sup.- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p.sup.- -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p.sup.- -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.
    Type: Grant
    Filed: April 2, 1991
    Date of Patent: August 26, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toyoki Takemoto, Haruyasu Yamada, Tsutomu Fujita, Tadao Komeda
  • Patent number: 5555527
    Abstract: A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: September 10, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisakazu Kotani, Hironori Akamatsu, Tsutomu Fujita
  • Patent number: 5232401
    Abstract: An air supplying apparatus for supplying a clean room with air having a conditioned cleanliness, temperature and/or humidity includes an air control unit for discharging the controlled air, and an air outlet duct connected to an air outlet of the air control unit so as to receive the conditioned air from the air control unit through an opening which opens in a direction different from the direction of flow of air through the air control unit. The air outlet duct is formed from one or more perforated sheets having a multiplicity of air outlet apertures. The cross-sectional area of the air passage formed in the air outlet duct preferably progressively decreases towards the downstream end of the duct. A joint duct, which guides air in a direction different from the directions of flow of air through the air control unit and through the air outlet duct, may be connected between the air control unit and the air outlet duct.
    Type: Grant
    Filed: April 20, 1992
    Date of Patent: August 3, 1993
    Assignees: Kawasaki Steel Corporation, Hirayama Setsubi Co., Ltd.
    Inventors: Tsutomu Fujita, Akira Sueda, Masao Kimura, Hitoshi Ura, Yotsuo Mizunuma, Misao Osawa
  • Patent number: 5109407
    Abstract: A communication device such as a video telephone is connected to a telephone line together with a telephone set at both parties. In response to an operation for removing a handset from a hook of the telephone set at this party, the video telephone at this party is initiated. Each of the video telephones includes a mode selecting switch and DTMF receiver which receives a DTMF signal from one of the telephone sets and decodes a received DTMF signal to output data representative of the mode of the video telephone. When a flag "1" is set, a mode of the video telephone at this party can be controlled in response to the DTMF signal which is received by the DTMF receiver from the telephone set at this party and, when a flat "2" is set a mode of the video telephone at this party can be controlled in response to the DTMF signal which is received by the DTMF receiver from the telephone set at the other party.
    Type: Grant
    Filed: December 19, 1989
    Date of Patent: April 28, 1992
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tsutomu Fujita, Yoshinobu Ido, Tsuneyoshi Yamada
  • Patent number: 5104826
    Abstract: In a CVD contact formed on a shallow junction having a depth of 0.2 micron or less, the presence of aluminum generates a leakage current at the junction after heat treatment. In order to restrain the leakage current, a barrier metal is formed below the aluminum electrode to form an Al/barrier metal/CVDW (tungsten) structure. A contact free from junction leakage and having a high aspect ratio is thereby realized.
    Type: Grant
    Filed: January 26, 1990
    Date of Patent: April 14, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsutomu Fujita, Toyokazu Fujii
  • Patent number: 5084413
    Abstract: A method for filling a contact hole in which (i) a silicon dioxide layer is formed on a silicon substrate; (ii) a contact hole is formed in the silicon dioxide layer; (iii) polysilicon film is formed on the side and bottom surface portions of the contact hole; (iv) gas containing tungsten reacts with the film; and (v) the contact hole is filled up with tungsten.
    Type: Grant
    Filed: May 29, 1990
    Date of Patent: January 28, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsutomu Fujita, Takao Kakiuchi, Hiroshi Yamamoto, Shoichi Tanimura