Patents by Inventor Tsutomu Murakawa
Tsutomu Murakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250248071Abstract: A semiconductor device that can be miniaturized or highly integrated includes an oxide semiconductor layer, first to third insulating layers, and first to third conductive layers. The first and second conductive layers are over the first insulating layer to be apart from each other. The first insulating layer includes a groove portion between the first and second conductive layers. The oxide semiconductor layer includes regions in contact with top and side surfaces of the first conductive layer, in contact with top and side surfaces of the second conductive layer, and in contact with a side surface of the groove portion. The second insulating layer is over the oxide semiconductor layer. The third conductive layer is over the second insulating layer. The third insulating layer includes a region in contact with the side surfaces of the oxide semiconductor layer, the second insulating layer, and the third conductive layer.Type: ApplicationFiled: January 28, 2025Publication date: July 31, 2025Inventors: Shunpei YAMAZAKI, Tsutomu MURAKAWA, Hidekazu MIYAIRI, Yasuhiro JINBO, Fumito ISAKA, Motomu KURATA
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Publication number: 20250234505Abstract: A semiconductor device with high field-effect mobility is provided. The semiconductor device includes an oxide semiconductor; a first conductor and a second conductor separated from each other over the oxide semiconductor; a first insulator that are placed over the first conductor and the second conductor and includes an opening overlapping with a region between the first conductor and the second conductor; a second insulator that is placed in the opening in the first insulator and is in contact with the top surface of the oxide semiconductor, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the first insulator; and a third conductor that is placed over the second insulator in the opening in the first insulator and includes a region overlapping with the oxide semiconductor with the second insulator therebetween.Type: ApplicationFiled: January 3, 2025Publication date: July 17, 2025Inventors: Hiromi SAWAI, Motomu KURATA, Tsutomu MURAKAWA, Sachiaki TEZUKA, Fumito ISAKA, Shunpei YAMAZAKI
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Publication number: 20250203944Abstract: A semiconductor device with less variations in transistor characteristics is provided. The semiconductor device includes: a first insulator; a first oxide over the first insulator; a first conductor and a second conductor over the first oxide; a first layer and a second layer which are in contact with a side surface of the first oxide; a second insulator over the first insulator, the first layer, the second layer, the first conductor, and the second conductor; a third insulator over the second insulator; a second oxide between the first conductor and the second conductor and over the first oxide; a fourth insulator over the second oxide; and a third conductor over the fourth insulator. Each of the first layer and the second layer includes a metal contained in the first conductor and the second conductor. The first insulator in a region in contact with the second insulator includes a region where a concentration of the metal is lower than that of the first layer or the second layer.Type: ApplicationFiled: March 6, 2025Publication date: June 19, 2025Inventors: Shunpei YAMAZAKI, Tsutomu MURAKAWA, Yoshinori ANDO, Tetsuya KAKEHATA, Yuichi SATO, Ryota HODO
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Patent number: 12283632Abstract: A semiconductor device with less variations in transistor characteristics is provided. The semiconductor device includes: a first insulator; a first oxide over the first insulator; a first conductor and a second conductor over the first oxide; a first layer and a second layer which are in contact with a side surface of the first oxide; a second insulator over the first insulator, the first layer, the second layer, the first conductor, and the second conductor; a third insulator over the second insulator; a second oxide between the first conductor and the second conductor and over the first oxide; a fourth insulator over the second oxide; and a third conductor over the fourth insulator. Each of the first layer and the second layer includes a metal contained in the first conductor and the second conductor. The first insulator in a region in contact with the second insulator includes a region where a concentration of the metal is lower than that of the first layer or the second layer.Type: GrantFiled: April 28, 2020Date of Patent: April 22, 2025Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tsutomu Murakawa, Yoshinori Ando, Tetsuya Kakehata, Yuichi Sato, Ryota Hodo
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Publication number: 20250081537Abstract: A semiconductor device in which a variation of transistor characteristics is small is provided. The semiconductor device includes a transistor. The transistor includes a first insulator, a first oxide over the first insulator, a first conductor, a second conductor, and a second oxide, which is positioned between the first conductor and the second conductor, over the first oxide, a second insulator over the second oxide, and a third conductor over the second insulator. A top surface of the first oxide in a region overlapping with the third conductor is at a lower position than a position of a top surface of the first oxide in a region overlapping with the first conductor. The first oxide in the region overlapping with the third conductor has a curved surface between a side surface and the top surface of the first oxide, and the curvature radius of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.Type: ApplicationFiled: November 18, 2024Publication date: March 6, 2025Inventors: Shunpei YAMAZAKI, Shinya SASAGAWA, Katsuaki TOCHIBAYASHI, Tsutomu MURAKAWA, Erika TAKAHASHI
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Publication number: 20250081424Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes first and second transistors. The first transistor includes a semiconductor layer, a pair of first conductive layers, and a pair of second conductive layers over the pair of first conductive layers. The pair of first conductive layers and the pair of second conductive layers function as a source electrode and a drain electrode of the first transistor. A third conductive layer functioning as a gate electrode of the second transistor is in contact with one of the pair of first conductive layers. In a cross-sectional view of the first transistor in the channel width direction, the height of the semiconductor layer is larger than the width of the semiconductor layer. The semiconductor device can include a capacitor, in which the third conductive layer also functions as one of a pair of electrodes.Type: ApplicationFiled: August 27, 2024Publication date: March 6, 2025Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tsutomu MURAKAWA, Hiromi SAWAI, Motomu KURATA, Sachiaki TEZUKA, Jun YAMADA, Shunpei YAMAZAKI
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Patent number: 12218246Abstract: A semiconductor device in which a variation of transistor characteristics is small is provided. The semiconductor device includes a transistor. The transistor includes a first insulator, a first oxide over the first insulator, a first conductor, a second conductor, and a second oxide, which is positioned between the first conductor and the second conductor, over the first oxide, a second insulator over the second oxide, and a third conductor over the second insulator. A top surface of the first oxide in a region overlapping with the third conductor is at a lower position than a position of a top surface of the first oxide in a region overlapping with the first conductor. The first oxide in the region overlapping with the third conductor has a curved surface between a side surface and the top surface of the first oxide, and the curvature radius of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.Type: GrantFiled: November 19, 2019Date of Patent: February 4, 2025Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Shinya Sasagawa, Katsuaki Tochibayashi, Tsutomu Murakawa, Erika Takahashi
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Publication number: 20250016973Abstract: A low-cost semiconductor device is provided. A memory cell including a first transistor, a second transistor, and a capacitor is provided. The second transistor is located above the first transistor and the capacitor. In the capacitor, one of a pair of electrodes, a dielectric layer, and the other of the pair of electrodes are provided in this order. A gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and the other of the pair of electrodes of the capacitor are the same conductive layer. A gate insulating layer of the first transistor and the dielectric layer of the capacitor are the same insulating layer. A semiconductor layer of the first transistor and the one of the pair of electrodes of the capacitor are provided along a sidewall of an opening portion included in a first interlayer insulating layer.Type: ApplicationFiled: July 1, 2024Publication date: January 9, 2025Inventors: Shunpei YAMAZAKI, Tsutomu MURAKAWA, Kentaro HAYASHI
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Publication number: 20250015193Abstract: Provided are a transistor with favorable electrical characteristics, a transistor with a high on-state current, a transistor with low parasitic capacitance, or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated. An oxide semiconductor layer included in the transistor, the semiconductor device, or the memory device includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron 10 microscope, bright spots arranged in a layered manner in a direction parallel to the surface are observed in each of the first region, the second region, and the third region.Type: ApplicationFiled: June 20, 2024Publication date: January 9, 2025Inventors: Shunpei YAMAZAKI, Fumito ISAKA, Yuichi SATO, Toshikazu OHNO, Hitoshi KUNITAKE, Tsutomu MURAKAWA
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Publication number: 20250015089Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, a first metal oxide, a first conductor, a second conductor, and a third conductor. The first metal oxide includes a first depressed portion, a second depressed portion, and a third depressed portion positioned between the first depressed portion and the second depressed portion. The first conductor is provided to fill the first depressed portion, and the second conductor is provided to fill the second depressed portion. A top surface of the first conductor and a top surface of the second conductor are level with or substantially level with a top surface of the first metal oxide. The first insulator is provided inside the third depressed portion. The third conductor is provided over the first insulator and includes a region overlapping with the first metal oxide with the first insulator therebetween.Type: ApplicationFiled: November 17, 2022Publication date: January 9, 2025Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei YAMAZAKI, Hitoshi KUNITAKE, Ryota HODO, Tsutomu MURAKAWA
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Publication number: 20250015194Abstract: A transistor that can be miniaturized is provided. The semiconductor device includes an oxide semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers. Over the first conductive layer including a depressed portion, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer which include a first opening portion overlapping with the depressed portion are provided in this order. The third insulating layer is in contact with at least the side surface of the second conductive layer in the first opening portion. The oxide semiconductor layer is in contact with the top surface of the third conductive layer and the bottom and side surfaces of the depressed portion, and is in contact with the third insulating layer in the first opening portion. The fourth insulating layer is on an inner side of the oxide semiconductor layer in the first opening portion.Type: ApplicationFiled: July 3, 2024Publication date: January 9, 2025Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei YAMAZAKI, Tsutomu Murakawa, Fumito Isaka, Hitoshi Kunitake, Yasuhiro Jinbo
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Publication number: 20250015195Abstract: A semiconductor device including an oxide semiconductor layer which is formed over a substrate and includes indium is provided. The oxide semiconductor layer is formed in parallel or substantially in parallel with a surface of the substrate. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a formation surface of the oxide semiconductor layer to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the formation surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the formation surface are observed in each of the first region, the second region, and the third region.Type: ApplicationFiled: July 3, 2024Publication date: January 9, 2025Inventors: Shunpei YAMAZAKI, Fumito ISAKA, Yuichi SATO, Toshikazu OHNO, Hitoshi KUNITAKE, Tsutomu MURAKAWA
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Patent number: 12176439Abstract: A semiconductor device with small fluctuations in transistor characteristics can be provided. The semiconductor device includes a first oxide, a second oxide and a third oxide over the first oxide, a first conductor over the second oxide, a second conductor over the third oxide, a fourth oxide over the first oxide and between the second oxide and the third oxide, a first insulator over the fourth oxide, and a third conductor over the first insulator. The first oxide includes a groove in a region not overlapping with the second oxide and the third oxide. The first oxide includes a first layered crystal substantially parallel to the surface where the first oxide is formed. In the groove, the fourth oxide includes a second layered crystal substantially parallel to the surface where the first oxide is formed. A concentration of aluminum atoms at an interface between the first oxide and the fourth oxide and in the vicinity of the interface is less than or equal to 5.0 atomic %.Type: GrantFiled: February 13, 2020Date of Patent: December 24, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Erika Takahashi, Tsutomu Murakawa, Shinya Sasagawa, Katsuaki Tochibayashi
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Publication number: 20240404884Abstract: To provide a semiconductor device with less variations, a first insulator is deposited; a stack of first and second oxides and a first conductor is formed over the first insulator; a second insulator is formed over the first insulator and the stack; an opening is formed in the second insulator; a top surface of the second oxide is exposed by removing a region of the first conductor, second and third conductors are formed over the second oxide, and then cleaning is performed; a first oxide film is deposited in contact with a side surface of the first oxide and top and side surfaces of the second oxide; heat treatment is performed on an interface between the second oxide and the first oxide film through the first oxide film; and the second insulator is exposed and a fourth conductor, a third insulator, and a third oxide are formed in the opening.Type: ApplicationFiled: August 9, 2024Publication date: December 5, 2024Inventors: Shunpei YAMAZAKI, Tsutomu MURAKAWA, Shinya SASAGAWA, Naoto YAMADE, Takashi HAMADA, Hiroki KOMAGATA
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Publication number: 20240395940Abstract: A transistor with high electrical characteristics is provided. A transistor with a high on-state current is provided. A transistor with small parasitic capacitance is provided. A transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated is provided. The transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer over the semiconductor layer, and a gate electrode over the gate insulating layer. A first insulating layer is between the first conductive layer and the second conductive layer. The second conductive layer is over the first insulating layer. The first insulating layer and the second conductive layer include an opening portion reaching the first conductive layer. The semiconductor layer is in contact with a sidewall of the opening portion. The semiconductor layer includes a first oxide layer and a second oxide layer. The first oxide layer includes a first region and a second region.Type: ApplicationFiled: May 15, 2024Publication date: November 28, 2024Inventors: Shunpei YAMAZAKI, Fumito ISAKA, Yuichi SATO, Toshikazu OHNO, Hitoshi KUNITAKE, Tsutomu MURAKAWA
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Patent number: 12154827Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.Type: GrantFiled: October 24, 2023Date of Patent: November 26, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toshihiko Takeuchi, Tsutomu Murakawa, Hiroki Komagata, Daisuke Matsubayashi, Noritaka Ishihara, Yusuke Nonaka
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Publication number: 20240379869Abstract: A semiconductor device includes an oxide semiconductor layer, first to third conductive layers, and first to third insulating layers. The first conductive layer includes a first depressed portion. The first insulating layer over the first conductive layer and the second conductive layer over the first insulating layer include a first opening portion overlapping with the first depressed portion. The oxide semiconductor layer is in contact with a top surface of the second conductive layer, bottom and side surfaces of the first depressed portion, a side surface of the second conductive layer, and a side surface of the first insulating layer. The second insulating layer is positioned inside the oxide semiconductor layer in the first opening portion. The third insulating layer covers top and side surfaces of the oxide semiconductor layer over the first insulating layer, and includes a second opening portion overlapping with the first opening portion.Type: ApplicationFiled: May 7, 2024Publication date: November 14, 2024Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Motomu KURATA, Ryota HODO, Yasuhiro JINBO, Tsutomu MURAKAWA, Satoru SAITO, Shunpei YAMAZAKI
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Patent number: 12068198Abstract: To provide a semiconductor device with less variations, a first insulator is deposited; a stack of first and a second oxides and a first conductor is formed over the first insulator; a second insulator is formed over the first insulator and the stack; an opening is formed in the second insulator; a top surface of the second oxide is exposed by removing a region of the first conductor, second and third conductors are formed over the second oxide, and then cleaning treatment is performed; a first oxide film is deposited in contact with a side surface of the first oxide and top and side surfaces of the second oxide; heat treatment is performed on an interface between the second oxide and the first oxide film through the first oxide film; and the second insulator is exposed and a fourth conductor, a third insulator, and a third oxide are formed in the opening.Type: GrantFiled: April 27, 2020Date of Patent: August 20, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tsutomu Murakawa, Shinya Sasagawa, Naoto Yamade, Takashi Hamada, Hiroki Komagata
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Publication number: 20240088232Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer and the second layer each include a transistor. The transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor over the first oxide, a first insulator placed to cover the first conductor, the second conductor, and the first oxide, a second insulator over the first insulator, a second oxide placed between the first conductor and the second conductor over the first oxide, a third insulator over the second oxide, a third conductor over the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Kosei NEI, Tsutomu MURAKAWA, Toshihiko TAKEUCHI, Kentaro SUGAYA
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Publication number: 20240055299Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Daisuke MATSUBAYASHI, Noritaka ISHIHARA, Yusuke NONAKA