Patents by Inventor Tsutomu Murakawa
Tsutomu Murakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088232Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer and the second layer each include a transistor. The transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor over the first oxide, a first insulator placed to cover the first conductor, the second conductor, and the first oxide, a second insulator over the first insulator, a second oxide placed between the first conductor and the second conductor over the first oxide, a third insulator over the second oxide, a third conductor over the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Kosei NEI, Tsutomu MURAKAWA, Toshihiko TAKEUCHI, Kentaro SUGAYA
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Publication number: 20240055299Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Daisuke MATSUBAYASHI, Noritaka ISHIHARA, Yusuke NONAKA
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Patent number: 11881513Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer and the second layer each include a transistor. The transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor over the first oxide, a first insulator placed to cover the first conductor, the second conductor, and the first oxide, a second insulator over the first insulator, a second oxide placed between the first conductor and the second conductor over the first oxide, a third insulator over the second oxide, a third conductor over the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor.Type: GrantFiled: April 16, 2019Date of Patent: January 23, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kosei Nei, Tsutomu Murakawa, Toshihiko Takeuchi, Kentaro Sugaya
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Publication number: 20240006539Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.Type: ApplicationFiled: September 15, 2023Publication date: January 4, 2024Inventors: Shunpei YAMAZAKI, Hiromi SAWAI, Ryo TOKUMARU, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Sho NAGAMATSU, Tomoaki MORIWAKA
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Patent number: 11830951Abstract: A semiconductor device with high productivity is provided. The semiconductor device includes a first and a second transistor and a first and a second capacitor. The first and the second transistor include gate electrodes and back gate electrodes. The second transistor is provided in a layer above the first transistor, and the second capacitor is provided in a layer above the first capacitor. One electrode of the first capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor and electrically connected to one of a source electrode and a drain electrode of the second transistor. The other electrode of the first capacitor is formed in the same layer as the back gate electrode of the second transistor.Type: GrantFiled: February 27, 2020Date of Patent: November 28, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuichi Yanagisawa, Hisao Ikeda, Tsutomu Murakawa
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Patent number: 11817507Abstract: A semiconductor device having a high on-state current is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor provided over the first oxide to be separated from each other; and a second oxide provided over the first oxide and between the first conductor and the second conductor. Each of the first oxide and the second oxide has crystallinity, the first oxide includes a region where a c-axis is aligned substantially perpendicularly to a top surface of the first oxide, and the second oxide includes a region where the c-axis is aligned substantially perpendicularly to the top surface of the first oxide, a region where the c-axis is aligned substantially perpendicularly to a side surface of the first conductor, and a region where the c-axis is aligned substantially perpendicularly to a side surface of the second conductor.Type: GrantFiled: February 9, 2022Date of Patent: November 14, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tsutomu Murakawa, Hiroki Komagata, Katsuaki Tochibayashi, Kentaro Sugaya
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Patent number: 11804407Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.Type: GrantFiled: November 4, 2021Date of Patent: October 31, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toshihiko Takeuchi, Tsutomu Murakawa, Hiroki Komagata, Daisuke Matsubayashi, Noritaka Ishihara, Yusuke Nonaka
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Patent number: 11784259Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.Type: GrantFiled: March 17, 2022Date of Patent: October 10, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiromi Sawai, Ryo Tokumaru, Toshihiko Takeuchi, Tsutomu Murakawa, Sho Nagamatsu, Tomoaki Moriwaka
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Publication number: 20230262952Abstract: A semiconductor device with a small variation in transistor characteristics can be provided. A step of forming an opening in a structure body including an oxide semiconductor device to reach the oxide semiconductor device, a step of embedding a first conductor in the opening, a step of forming a second conductor in contact with a top surface of the first conductor, a step of forming a first barrier insulating film by a sputtering method to cover the structure body, the first conductor, and the second conductor, and a step of forming a second barrier insulating film over the first barrier insulating film by an ALD method are included. The first barrier insulating film and the second barrier insulating film each have a function of inhibiting hydrogen diffusion.Type: ApplicationFiled: August 5, 2021Publication date: August 17, 2023Inventors: Shunpei YAMAZAKI, Motomu KURATA, Tsutomu MURAKAWA, Ryo ARASAWA, Kunihiro FUKUSHIMA, Yasumasa YAMANE, Shinya SASAGAWA
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Publication number: 20220399370Abstract: A highly reliable memory device is provided.Type: ApplicationFiled: November 9, 2020Publication date: December 15, 2022Inventors: Hiromi SAWAI, Tsutomu MURAKAWA, Hitoshi KUNITAKE
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Publication number: 20220336670Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.Type: ApplicationFiled: March 17, 2022Publication date: October 20, 2022Inventors: Shunpei YAMAZAKI, Hiromi SAWAI, Ryo TOKUMARU, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Sho NAGAMATSU, Tomoaki MORIWAKA
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Publication number: 20220271169Abstract: A semiconductor device having a high on-state current is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor provided over the first oxide to be separated from each other; and a second oxide provided over the first oxide and between the first conductor and the second conductor. Each of the first oxide and the second oxide has crystallinity, the first oxide includes a region where a c-axis is aligned substantially perpendicularly to a top surface of the first oxide, and the second oxide includes a region where the c-axis is aligned substantially perpendicularly to the top surface of the first oxide, a region where the c-axis is aligned substantially perpendicularly to a side surface of the first conductor, and a region where the c-axis is aligned substantially perpendicularly to a side surface of the second conductor.Type: ApplicationFiled: February 9, 2022Publication date: August 25, 2022Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Katsuaki TOCHIBAYASHI, Kentaro SUGAYA
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Publication number: 20220246763Abstract: A semiconductor device with less variations in transistor characteristics is provided. The semiconductor device includes: a first insulator; a first oxide over the first insulator; a first conductor and a second conductor over the first oxide; a first layer and a second layer which are in contact with a side surface of the first oxide; a second insulator over the first insulator, the first layer, the second layer, the first conductor, and the second conductor; a third insulator over the second insulator; a second oxide between the first conductor and the second conductor and over the first oxide; a fourth insulator over the second oxide; and a third conductor over the fourth insulator. Each of the first layer and the second layer includes a metal contained in the first conductor and the second conductor. The first insulator in a region in contact with the second insulator includes a region where a concentration of the metal is lower than that of the first layer or the second layer.Type: ApplicationFiled: April 28, 2020Publication date: August 4, 2022Inventors: Shunpei YAMAZAKI, Tsutomu MURAKAWA, Yoshinori ANDO, Tetsuya KAKEHATA, Yuichi SATO, Ryota HODO
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Publication number: 20220208988Abstract: A semiconductor device with less variations in transistor characteristics is provided.Type: ApplicationFiled: April 27, 2020Publication date: June 30, 2022Inventors: Shunpei YAMAZAKI, Tsutomu MURAKAWA, Shinya SASAGAWA, Naoto YAMADE, Takashi HAMADA, Hiroki KOMAGATA
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Publication number: 20220157992Abstract: A semiconductor device with high productivity is provided. The semiconductor device includes a first and a second transistor and a first and a second capacitor. The first and the second transistor include gate electrodes and back gate electrodes. The second transistor is provided in a layer above the first transistor, and the second capacitor is provided in a layer above the first capacitor. One electrode of the first capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor and electrically connected to one of a source electrode and a drain electrode of the second transistor. The other electrode of the first capacitor is formed in the same layer as the back gate electrode of the second transistor.Type: ApplicationFiled: February 27, 2020Publication date: May 19, 2022Inventors: Yuichi YANAGISAWA, Hisao IKEDA, Tsutomu MURAKAWA
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Patent number: 11282964Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.Type: GrantFiled: November 26, 2018Date of Patent: March 22, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiromi Sawai, Ryo Tokumaru, Toshihiko Takeuchi, Tsutomu Murakawa, Sho Nagamatsu, Tomoaki Moriwaka
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Publication number: 20220077317Abstract: A semiconductor device in which a variation of transistor characteristics is small is provided. The semiconductor device includes a transistor. The transistor includes a first insulator, a first oxide over the first insulator, a first conductor, a second conductor, and a second oxide, which is positioned between the first conductor and the second conductor, over the first oxide, a second insulator over the second oxide, and a third conductor over the second insulator. A top surface of the first oxide in a region overlapping with the third conductor is at a lower position than a position of a top surface of the first oxide in a region overlapping with the first conductor. The first oxide in the region overlapping with the third conductor has a curved surface between a side surface and the top surface of the first oxide, and the curvature radius of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.Type: ApplicationFiled: November 19, 2019Publication date: March 10, 2022Inventors: Shunpei YAMAZAKI, Shinya SASAGAWA, Katsuaki TOCHIBAYASHI, Tsutomu MURAKAWA, Erika TAKAHASHI
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Publication number: 20220077322Abstract: A semiconductor device with small fluctuations in transistor characteristics can be provided. The semiconductor device includes a first oxide, a second oxide and a third oxide over the first oxide, a first conductor over the second oxide, a second conductor over the third oxide, a fourth oxide over the first oxide and between the second oxide and the third oxide, a first insulator over the fourth oxide, and a third conductor over the first insulator. The first oxide includes a groove in a region not overlapping with the second oxide and the third oxide. The first oxide includes a first layered crystal substantially parallel to the surface where the first oxide is formed. In the groove, the fourth oxide includes a second layered crystal substantially parallel to the surface where the first oxide is formed. A concentration of aluminum atoms at an interface between the first oxide and the fourth oxide and in the vicinity of the interface is less than or equal to 5.0 atomic %.Type: ApplicationFiled: February 13, 2020Publication date: March 10, 2022Inventors: Shunpei YAMAZAKI, Erika TAKAHASHI, Tsutomu MURAKAWA, Shinya SASAGAWA, Katsuaki TOCHIBAYASHI
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Publication number: 20220059409Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Daisuke MATSUBAYASHI, Noritaka ISHIHARA, Yusuke NONAKA
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Patent number: 11257959Abstract: A semiconductor device having a high on-state current is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor provided over the first oxide to be separated from each other; and a second oxide provided over the first oxide and between the first conductor and the second conductor. Each of the first oxide and the second oxide has crystallinity, the first oxide includes a region where a c-axis is aligned substantially perpendicularly to a top surface of the first oxide, and the second oxide includes a region where the c-axis is aligned substantially perpendicularly to the top surface of the first oxide, a region where the c-axis is aligned substantially perpendicularly to a side surface of the first conductor, and a region where the c-axis is aligned substantially perpendicularly to a side surface of the second conductor.Type: GrantFiled: November 28, 2018Date of Patent: February 22, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tsutomu Murakawa, Hiroki Komagata, Katsuaki Tochibayashi, Kentaro Sugaya