Patents by Inventor Tsutomu Yamada

Tsutomu Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040087067
    Abstract: A first contact hole (6) is formed penetrating a gate insulating film (5), on which a gate electrode (7g) is formed and simultaneously a first contact (7s, 7d) is formed in the first contact hole. A second contact hole (9) penetrating an interlayer insulating film (8) is formed, and a second contact (10) is formed in the second contact hole (9). A third contact hole (11) is formed penetrating a planarization film (26), and an electrode (40) is formed in the third contact hole (11). By using a plurality of contact holes for electrically connecting the electrode (40) and a semiconductor film (3), the aspect ratio of each contact hole can be reduced, thereby achieving improvement in yield, high-level integration due to a reduction in difference in area between upper and bottom surfaces of the contact, and other advantageous improvements.
    Type: Application
    Filed: January 16, 2003
    Publication date: May 6, 2004
    Inventors: Kiyoshi Yoneda, Tsutomu Yamada, Shinji Yuda, Koji Suzuki
  • Patent number: 6728811
    Abstract: There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Yamada, Kenichi Kurosawa, Yasuo Kaminaga, Kouji Masui, Akihiro Ohashi
  • Patent number: 6727871
    Abstract: Side faces of anodes have a tapered incline that becomes broader toward a lower layer. Thus, an emissive element layer is smoothly formed on the anodes making it possible to prevent field contraction of the electric field. An EL display apparatus having long life and high yield is provided by preventing the emissive element layer from rupturing between an anode and a cathode and by preventing concentration of the electric field at an upper edge of the anode facing the cathode and localized deterioration in the emissive element layer.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: April 27, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Koji Suzuki, Tsutomu Yamada
  • Patent number: 6724149
    Abstract: Power source lines (183) for supplying drive current from power source input terminals (180) to organic EL elements (160) formed in a display pixel region having display pixels are connected by a bypass line (181) along the row direction within the display pixel region. This arrangement minimizes decrease in power source current caused by resistance of the power source lines (183) according to the line length. Accordingly, the organic EL elements (160) can adequately receive the actual desired current, thereby achieving an organic EL device capable of bright displays and having uniform display luminance within the display region.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: April 20, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Naoaki Komiya, Ryoichi Yokoyama, Tsutomu Yamada, Ryuji Nishikawa
  • Patent number: 6703992
    Abstract: In an active matrix type EL device, a semiconductor layer (intersection protective film F1, F2, F3, F4) is inserted between lines at an intersection of a gate line GL and a data line DL; an intersection of the gate line GL and a power source line VL; an intersection of a storage capacitor line CL and the data line DL; and an intersection of the storage capacitor line CL and the power source line VL for inter-line insulation. No impurities are doped in the regions corresponding to these intersections CR1˜CR4, to thereby maintain high resistance. The intersection protective films are integrally formed for the intersections CR1 and CR2 and for the intersections CR3 and CR4 and extend over the respective two intersections. With the above-described structure, it is possible to prevent short circuit or deterioration of voltage withstanding characteristics at the intersections on the panel where lines intersect, without a drastic increase in the number of processes.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: March 9, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Tsutomu Yamada
  • Publication number: 20040038501
    Abstract: In an active matrix type display having built-in drivers, a metal layer is formed over a portion of a transparent substrate and a buffer layer is provided over both the region where the metal layer is formed and over the region where the metal layer is not formed. Above the buffer layer, a first polycrystalline silicon film is provided over the region where the metal layer is formed and a second polycrystalline silicon film is provided over the region where the metal layer is not formed. A buffer layer with sufficient thickness and thermal capacity can provide sufficient distance between the active layers and the lower metal layer to alleviate thermal leakage caused by the metal layer. A first polycrystalline silicon film and a second polycrystalline film each having a proper grain size can be obtained through laser annealing applied under the same conditions on an amorphous silicon film formed over the buffer layer.
    Type: Application
    Filed: July 11, 2003
    Publication date: February 26, 2004
    Inventor: Tsutomu Yamada
  • Patent number: 6690110
    Abstract: A wide line portion is extended from a cathode and another wide line portion is formed by second lines extending from cathode terminals. A contact CN1, which is also wide, is formed to connect both wide line portions in a portion where two wide line portions overlap, with an insulating film being interposed therebetween. Further, fifth line connected to the wide line portion is contact with the cathode at second contacts provided in the periphery of the display region. IN these contacts, an intermediate layer composed of a conductive oxide material is interposed, to thereby prevent deterioration of display quality by preventing reduction of a voltage applied to the cathode due to increased line resistance between the terminals and the cathode.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: February 10, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tsutomu Yamada, Masahiro Okuyama
  • Patent number: 6686215
    Abstract: An emissive element layer (65) composed of an organic compound is formed on an anode (61) of an organic EL element or the like, using an evaporation mask (150) in which the width d of an opening (151) and the thickness h of the mask (150) satisfy the relationship h>n×d, Where n>1, and more preferably 1<n≦2.5. Accordingly, an EL display device can be obtained in which outspread of an emissive layer material onto an adjacent pixel electrode can be prevented to thereby reduce color mixture.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: February 3, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Tsutomu Yamada
  • Publication number: 20040016924
    Abstract: In a top gate type TFT wherein a gate electrode is formed above an active layer, an interlayer insulating film formed so as to cover a TFT active layer, a gate insulating film, and a gate electrode have a structure configured by laminating a SiNx film and a SiO2 film, in that order from an active layer side. The thickness of the SiNx film is between 50 nm-200 nm, more preferably on the order of 100 nm. Employing such a thickness ensures that a sufficient amount of hydrogen for terminating dangling bonds can be supplied to the active layer made of a semiconductor such as polycrystalline Si provided as a lower layer. Further, a higher accuracy of contact holes or the like formed in the interlayer insulating film can be assured.
    Type: Application
    Filed: March 10, 2003
    Publication date: January 29, 2004
    Inventors: Tsutomu Yamada, Yasuo Segawa, Masaaki Aota
  • Publication number: 20040007183
    Abstract: This thin film-forming apparatus comprises a vacuum chamber 2 for forming a thin film on a target material 5, an evaporation source 3 arranged in the chamber 2 and having an evaporation port 33 through which the vapor of a material 40 to be vapor-deposited passes, and a moving mechanism 20 for moving the source 3 towards the widthwise direction of the port 33 between a prescribed waiting position and film-forming position of the source 3. This apparatus further comprises a film-thickness sensor 50 for detecting a film-forming speed of the material 40, which is arranged in a vicinity of the waiting position of the source 3 and on a side of the material 5. The source 3 is positioned opposite to the sensor 50 at the waiting position and is positioned opposite to the material 5 at the film-forming position.
    Type: Application
    Filed: July 11, 2002
    Publication date: January 15, 2004
    Applicant: ULVAC, Inc.
    Inventors: Steven Van Slyke, Tsutomu Yamada, Ryuji Nishikawa, Hiroshi Kanno, Hisakazu Takahashi, Yoshitaka Nishio, Toshio Negishi
  • Publication number: 20040006401
    Abstract: The invention contemplates to improve versatility or flexibility of a system for managing a controller. In a data format converter, a computer constitutes reception unit for acquiring input information containing a program, etc, of a first data format and outputted from a programmer unit, direction extract unit for extracting a convert direction of a data format contained in the input information so acquired, data conversion rule acquisition unit for acquiring a conversion rule of a data format corresponding to the convert direction so extracted and convert execution means for converting the program, etc, of the first data format to a second data format. The program, etc, of the second data format converted is outputted to the controller. The program, etc, can be created in this way in an arbitrary data format different from the data format of the controller.
    Type: Application
    Filed: July 7, 2003
    Publication date: January 8, 2004
    Inventors: Tsutomu Yamada, Masahiko Saito, Shoji Suzuki, Hiromichi Endoh, Noritaka Matsumoto, Hirokazu Kasashima, Manabu Yamauchi
  • Publication number: 20040004686
    Abstract: A reflective layer for reflecting light incident from a second substrate side and transmitting through a second electrode made of ITO or the like is formed above a first substrate, a switching element provided for each pixel, and an insulating film covering the switching element, the reflective layer being insulated from the switching element. A first electrode having a work function similar to the second electrode and made of a transparent conductive material such as ITO is formed more proximate to a liquid crystal layer than is the reflective layer and is connected to the switching element. The thickness of the first electrode is set to 100 Å or less or in a range approximately from 750 Å to 1250 Å.
    Type: Application
    Filed: February 28, 2003
    Publication date: January 8, 2004
    Inventors: Shinji Ogawa, Kazuhiro Inoue, Norio Koma, Nobuhiko Oda, Satoshi Ishida, Tsutomu Yamada, Tohru Yamashita
  • Patent number: 6664563
    Abstract: An electroluminescence (EL) device is resistant to external shock and has a prolonged service life. In the device, an emissive element substrate has a first electrodes formed on a substrate, an emissive element layer formed over the first electrodes, and a second electrode formed on the emissive layer. A sealing member covers the second electrode of the emissive element substrate. Shock buffers in pillar, spherical, or sheet form are arranged in a gap between the second electrode and the sealing member. When the shock members are made of a hard material, they are preferably arranged above the non-emissive areas in the EL device.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: December 16, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tsutomu Yamada, Ryuji Nishikawa
  • Publication number: 20030228417
    Abstract: The evaporation method of this invention comprises a process for tightly placing an evaporation mask on a substrate, and a process for disposing an evaporation material on the surface of the substrate through a plurality of openings formed in the evaporation mask by moving a plurality evaporation sources along the entire length of the substrate for forming a pattern. The evaporation sources are loaded with different evaporation materials. A plurality of evaporation layers can be continuously disposed on the substrate by sequentially or simultaneously moving the evaporation source.
    Type: Application
    Filed: March 28, 2003
    Publication date: December 11, 2003
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Ryuji Nishikawa, Tsutomu Yamada
  • Patent number: 6628363
    Abstract: A circuit having a CMOS configuration in which n-type and p-type thin film transistors are connected in a complementary manner to one another is employed as a drive circuit of a display or the like. The n-type and p-type thin film transistors have common gate electrodes and drain electrodes, with respective source electrodes being connected to difference power sources, thereby providing a complementary connection structure. A source electrode of that one of the n-type thin film transistor and the p-type thin film transistor that is subjected for a longer period of time to an off voltage, applied to the shared gate electrode, for turning that transistor off, is extended in such a manner as to overlap a channel formation region of the corresponding thin film transistor. This present a variation in characteristic of the thin film transistor.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: September 30, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Keiichi Sano, Yasuo Segawa, Norio Tabuchi, Tsutomu Yamada
  • Patent number: 6621103
    Abstract: In an active matrix type display having built-in drivers, a metal layer is formed over a portion of a transparent substrate and a buffer layer is provided over both the region where the metal layer is formed and over the region where the metal layer is not formed. Above the buffer layer, a first polycrystalline silicon film is provided over the region where the metal layer is formed and a second polycrystalline silicon film is provided over the region where the metal layer is not formed. A buffer layer with sufficient thickness and thermal capacity can provide sufficient distance between the active layers and the lower metal layer to alleviate thermal leakage caused by the metal layer. A first polycrystalline silicon film and a second polycrystalline film each having a proper grain size can be obtained through laser annealing applied under the same conditions on an amorphous silicon film formed over the buffer layer.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: September 16, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Tsutomu Yamada
  • Patent number: 6613618
    Abstract: A thin-film transistor is provided in which the thickness of the insulating film is optimized. A gate electrode is formed on a transparent substrate. A silicon nitride film and a silicon oxide film, acting as a gate insulating film, are formed over the transparent substrate. A polycrystalline silicon film, being a semiconductor film, is formed acting as an active region. A stopper is formed on the polycrystalline silicon film corresponding to the gate electrode. A silicon oxide film and a silicon nitride film, acting as an interlayer insulating film, are deposited as to cover the stopper region. The total film thickness T1 of the stopper and the silicon oxide film is formed to be thinner than (the thickness T2 of the silicon nitride film×8000 Å)½.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: September 2, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shiro Nakanishi, Tsutomu Yamada
  • Patent number: 6614497
    Abstract: A liquid crystal display device comprising: a first substrate and a second substrate processed for vertical alignment; a liquid crystal having a negative dielectric constant anisotropy and being sandwiched between the first and second substrates; an array of first protrusions on the first substrate, each of the first protrusions being bent in zigzag, the first protrusions being arranged in parallel to one another with a predetermined pitch among them; a plurality of pixel electrodes on the second substrate; and an array of second protrusions or slits provided on the pixel electrodes, each extending in a direction, the second protrusions or slits being arranged in parallel to one another. The liquid crystal display device of the present invention is characterized that the angle included between the edge of the pixel electrodes and the extending direction of the second protrusions or slits is kept at least 135 degrees.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: September 2, 2003
    Assignee: Chi Mei Optoelectronics Corp.
    Inventor: Tsutomu Yamada
  • Publication number: 20030156239
    Abstract: On a first substrate, a TFT which is a switching element is provided for each pixel, and above an insulating film covering this TFT, a reflective layer which is insulated from the TFT and which reflects light entering a second substrate and transmitting through a second electrode made of ITO is formed. Further, a first electrode having a work function similar to that of the second electrode and made of a transparent conductive material such as ITO is formed closer to a liquid crystal layer than the reflective layer, and this first electrode is connected with the TFT. With this configuration, the liquid crystal layer can be symmetrically AC driven by the first and second electrodes. A reliable connection between the first electrode and the TFT is provided through a connection metal layer made of a refractory metal.
    Type: Application
    Filed: December 27, 2002
    Publication date: August 21, 2003
    Inventors: Kazuhiro Inoue, Norio Koma, Shinji Ogawa, Tohru Yamashita, Nobuhiko Oda, Satoshi Ishida, Tsutomu Yamada
  • Publication number: 20030156240
    Abstract: On a first substrate are formed a TFT provided to each pixel, an insulating film which covers the TFT, and a reflective layer which is provided on the insulating film so as to be insulated from the TFT and reflects light incident from a second substrate side. The reflective layer is covered with a passivation film on which a first electrode made of a transparent conductive material, such as ITO having the work function equivalent to a second electrode, is formed and connected to the TFT. The passivation film covering the reflective layer prevents the reflective surface of the reflective layer from deteriorating in reflection properties during a process for connecting the TFT and the first electrode. Further, the first and second electrodes having similar characteristics can symmetrically AC drive the liquid crystal layer.
    Type: Application
    Filed: December 27, 2002
    Publication date: August 21, 2003
    Inventors: Nobuhiko Oda, Satoshi Ishida, Tsutomu Yamada