Abstract: A processing module to use for a processing system having a plurality of processing modules connected via a communication line is comprising mounting position information for the processing module in the communication line; a unique logical address to indicate the processing module; a database to correspond with a physical address of the processing module in the communication line; a position identification device to identify the mounting position information in the communication line of the processing module; a unique/physical address conversion device to fetch the physical address corresponding to the unique logical address from the database using a data packet having the unique logical address as a destination; and a position/physical address conversion device for searching for the physical address from the mounting position information.

Abstract: An initialization data generator includes a task database in which task descriptions for initializing a computer are specified related with task IDs and an initialization database in which initialization data descriptions for initializing a computer are stored related with initialization data IDs. The initialization data generator takes input of the computer ID of a computer to be initialized and task data, reads task descriptions and initialization data descriptions according to task ordering related with the task data from the task database and the initialization database, based on the task IDs, task ordering, and the initialization data IDs for software modules which are loaded into the computer to be initialized by the tasks corresponding to the task IDs, specified in the task data, and generates and transfers initialization data to the computer to be initialized, thereby initializing the computer to be initialized.

Abstract: An input/output control apparatus including: a unit that controls input/output of data relating to a computation of a plurality of processors in response to an access request from a second input/output unit and an access request from a first input/output unit which requires higher reliability than said second input/output unit, and orders at least one of a plurality of processors to perform a computation relating to the access request from said first input/output unit away from the computation relating to the access request from said second input/output unit in case of that said first input/output unit issued an access request, so that a same computation is made by said plurality of processors; a unit that compares the results of said computations relative to the access request from said first input/output unit provided from said plurality of processors; and a unit that allows the data associated with said computations of said processors to be output on the basis of said compared results.

Abstract: An information processor capable of ensuring time synchronization accuracy, ensuring EtherCAT command consistency, and easily developing the software based on a 2-port configuration even when a communication path error occurs includes: an arithmetic section; at least two communication sections each including a transmission section and a reception section; and a redundant communication control section that controls a communication path between the arithmetic section and the communication section. The redundant communication control section includes: a communication path state determination section that determines a network path state; and a redundant path switching section that switches connection between the arithmetic section and at least two communication sections. The network provides a logical ring topology for a packet communication path.

Abstract: A control computer as a master apparatus in a control network system includes a packet generation unit. The packet generation unit: selects a control command for writing a data from among packet generation information; references the packet generation information for each of the selected control command; and includes a data for write which is read from an address in a storage section corresponding to the each control command, in a control packet to generate the control packet. A communication unit transmits the generated control packet to a controlled object as a slave device.

Abstract: A network system includes one or more terminals which transmit acquired data to a first network, a network interconnection device which is connected to the terminal via the first network and which receives the data from the terminal, and a management server which is connected to the network interconnection device via a second network and which receives the data from the network interconnection device; the terminal transmits the same data to the network interconnection device via the first network by a frequency corresponding to redundancy; the data contains the priority according to the contents of the data; and the network interconnection device acquires the communication quality of the second network and instructs the terminal to transmit the data according to redundancy determined based upon the acquired communication quality and the priority.

Abstract: A wireless communication system includes a wireless communication apparatus (fixed terminal) resided in a fixed station side providing a wireless antenna, a wireless communication unit, a server processing unit, a task list, a data communication unit, a buffer management unit and a buffer, and a wireless data transport apparatus (mobile terminal) resided in a mobile station side providing the wireless antenna, the wireless communication unit, a server determination unit, a task list I/O unit, the task list, a client processing unit and the buffer, thereby, the mobile terminal receives the task list from the fixed terminal to communicate data with another fixed terminal and transports not only the data but also a data acknowledgement, and the fixed terminal creates the acknowledgement to use the acknowledgement to thereby control a creation and deletion of bulk data appropriately.

Abstract: A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication.

Abstract: A modular computer system formed by connecting a processing module having a processor mounted thereon and a plurality of I/O modules in a stacked form via connectors, where differing ones of the plurality of I/O modules being differing types of I/O modules from one another, which operate with mutually differing types of bus-layout configurations. In accordance with the association of I/O modules with identification information, for each differing type of I/O module stacked via the connectors, said processing module selects from differing preset bus-layout configurations and device drivers from a memory, to dynamically reconfigure the reconfigurable generic bus for accessing the differing type of I/O module.

Abstract: A plurality of wireless communication methods are combined, networks to be used are dynamically selected by evaluating each network quality, and a packet format is changed adaptively to realize necessary reliability. The wireless communication apparatus has a network interface, a data interface, a quality interface, an allocation control part, a quality database, a quality update part, communication units and antennas. The wireless communication apparatus receives data and a requested quality from an application apparatus, selects the communication unit and communication method suitable for the requested quality, and transmits the data and requested quality. The communication unit receives a communication quality of the communication partner, and the quality update part updates the communication quality state in the quality database.

Abstract: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.

Abstract: The information processor includes a device communication performance management module. The device communication performance management module includes: a communication performance evaluation unit that measures and evaluates the communication performance with respect to a device to be used when it is used by a device-use application; a device naming rule management unit that manages a naming rule for incorporating the communication performance evaluated by the communication performance evaluation unit into the name of the device file for a device as the target of evaluation; and a device file management unit that creates a device file for a device as the target of evaluation in accordance with the naming rule based on the result of communication performance evaluation. The result of communication performance evaluation by the communication performance evaluation unit is incorporated into the name of a device file and the evaluation result is thereby provided to a device-use application.

Abstract: An information processor disclosed herein prevents adverse impacts on higher priority processing due to extremely frequent receive processing when inbound traffic from a network is over-traffic state (under a DoS attack). The information processor attached to a network collects information about traffic state and, if it is determined that over-traffic state is present, deactivates the communication processing function without passing an interrupt request due to communication to the data processing block. In this state, the information processor continues to collect information about traffic state and, when it is determined that over-traffic state has terminated, starts to transfer an interrupt request to the data processing block and makes the communication processing function recover.

Abstract: A feedback control device capable of continuously performing high-accuracy, stable control even in cases where any of multiple controllers for controlling a controlled system becomes incapable of control action. A controller (master controller) generates control data for stably controlling a heater by feedback control, controls the heater in accordance with the control data, and sends the control data to the other controller (slave controller). The slave controller receives the control data from the master controller but does not control the heater while the master controller is operating normally. If the master controller develops anomaly and becomes incapable of normal control action, the slave controller initiates feedback control of the heater in accordance with the control data received from the master controller immediately before the anomaly occurred, and controls the heater thereafter in accordance with control data generated thereby.

Abstract: In a touch panel, a rectangular resistive film is formed on a substrate and electrodes are provided along the four sides of the resistive film. Each electrode includes a plurality of gaps and a plurality of divided electrodes. The divided electrodes are linearly arranged along the corresponding side of the resistive film, and the electrode, in which the divided electrodes at both ends are connected to terminals, respectively, is formed by arranging the divided electrodes of the same shape and repeating this same shape.

Abstract: A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system including one system module and n peripheral modules, each peripheral module includes an interrupt selector, a clock selector, an arbitration signal selector, a resource decision unit, and a position identification unit. The position identification unit cooperates with a position configuration unit present in the system module to identify a position of the module, which includes the position identification unit, in the computer system, and autonomously decides bus resources used by the module. By allowing the interrupt selector, the clock selector, and the arbitration signal selector to select and use the decided bus resources, each peripheral module can match and configure the bus resources in the computer system.

Abstract: An interrupt control unit provides controls on an interrupt from an accelerator to a CPU based on a packet transmitted to or received from a controlled object. The interrupt control unit includes: a storage part for storing therein an interrupt control timing table in which a condition of switching a mode of the interrupt control is described; and an interrupt control mode switching part for switching the mode of the interrupt control to the CPU between a permission mode and a mask mode, based on the interrupt control timing table in the storage part.

Abstract: The invention contemplates to improve versatility or flexibility of a system for managing a controller. In a data format converter, a computer constitutes reception unit for acquiring input information containing a program, etc, of a first data format and outputted from a programmer unit, direction extract unit for extracting a convert direction of a data format contained in the input information so acquired, data conversion rule acquisition unit for acquiring a conversion rule of a data format corresponding to the convert direction so extracted and convert execution means for converting the program, etc, of the first data format to a second data format. The program, etc, of the second data format converted is outputted to the controller. The program, etc, can be created in this way in an arbitrary data format different from the data format of the controller.

Abstract: A vertical alignment liquid crystal layer is sealed between a first substrate having a first electrode and a second substrate having a second electrode, each pixel region has a reflective region and a transmissive region, and a gap adjusting section is provided on one of sides of the first substrate and the second substrate which sets a thickness (gap) d of the liquid crystal layer which controls a phase difference of incident light to the liquid crystal layer so that a gap dr in the reflective region is smaller than a gap dt in the transmissive region. An alignment controller which divides alignment of the liquid crystal within a pixel region is provided in the pixel region on at least one of the sides of the first substrate and the second substrate. It is also possible to optimize by changing the gap in red, green, and blue.

Abstract: The invention contemplates to improve versatility or flexibility of a system for managing a controller. In a data format converter, a computer constitutes reception unit for acquiring input information containing a program, etc, of a first data format and outputted from a programmer unit, direction extract unit for extracting a convert direction of a data format contained in the input information so acquired, data conversion rule acquisition unit for acquiring a conversion rule of a data format corresponding to the convert direction so extracted and convert execution means for converting the program, etc, of the first data format to a second data format. The program, etc, of the second data format converted is outputted to the controller. The program, etc, can be created in this way in an arbitrary data format different from the data format of the controller.