Abstract: The present invention relates to a method of producing a cellulose-fiber flat structure, the method including obtaining a cellulose-fiber flat structure by filtering a fine cellulose-fiber dispersion containing fine cellulose fibers having an average fiber diameter of 4 to 100 nm, using a filter material having a water permeability of not more than 100 ml/m2·s and an initial tensile modulus of 20 MPa or greater. The present invention is able to produce a cellulose-fiber flat structure by efficiently recovering fine cellulose fibers from a dispersion containing fine cellulose fibers having an average fiber diameter at the nano level. The method of producing a cellulose-fiber flat structure can also be applied to a continuous process.

Abstract: A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

Abstract: A center-channel protector for a vehicle sash door is arranged between a main sash and a center channel. A body of the protector has an H-shaped upper-end surface which is compatible to cover the upper end of the center channel. The body integrally includes a pair of branch covering portions corresponding to a pair of branch portions constituting the center channel and a middle covering portion disposed between the branch covering portions so as to connect the both branch covering portions therewith. An engaging portion is provided with the body and is mechanically engaged, in a direction intersecting a vertical direction, with an engaged portion which is provided with a center channel side. In collaboration with the engaged portion, the engaging portion constitutes a fastening mechanism by which the protector is fastened on the center channel.

Abstract: Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

Abstract: A resistor R1 formed by forming a first resistor layer 5a of 20 nm thickness including a tantalum nitride film at a concentration of nitrogen of less than 30 at % and a second resistor layer of 5 nm thickness including a tantalum nitride film at a concentration of nitrogen of 30 at % or more successively by a reactive DC sputtering method using tantalum as a sputtering target material and using a gas mixture of argon and nitrogen as a sputtering gas, and then fabricating the first and the second resistor layers, in which the resistance change ratio of the resistor can be suppressed to less than 1% even when a thermal load is applied in the interconnection step, by the provision of the upper region at a concentration of nitrogen of 30 at % or more.

Abstract: A center-channel protector for a vehicle sash door is arranged between a main sash and a center channel. A body of the protector has an H-shaped upper-end surface which is compatible to cover the upper end of the center channel. The body integrally includes a pair of branch covering portions corresponding to a pair of branch portions constituting the center channel and a middle covering portion disposed between the branch covering portions so as to connect the both branch covering portions therewith. An engaging portion is provided with the body and is mechanically engaged, in a direction intersecting a vertical direction, with an engaged portion which is provided with a center channel side. In collaboration with the engaged portion, the engaging portion constitutes a fastening mechanism by which the protector is fastened on the center channel.

Abstract: A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

Abstract: The present invention provides an MIM capacitor using a high-k dielectric film preventing degradation of breakdown field strength of the MIM capacitor and suppressing the increase of the leakage current. The MIM capacitor comprises a first metal interconnect, a fabricated capacitance film, a fabricated upper electrode, and a third metal interconnect. The MIM capacitor is realized by forming an interlayer dielectric film comprising silicon oxide so as to cover the first metal interconnect, then forming a first opening in the interlayer dielectric film to a region corresponding to a via hole layer in the interlayer dielectric film just above the first metal interconnect so as not to expose the upper surface of the first metal interconnect, then forming a second opening to the inside of the first opening so as to expose the surface of the first metal interconnect and then forming a capacitance film and a third metal interconnect.

Abstract: A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

Abstract: The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part.

Abstract: In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

Abstract: Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

Abstract: A vehicular door sash includes a sash frame formed by subjecting a predetermined metal sheet to a roll molding process to have a predetermined cross section. The sash frame includes a groove portion for retaining a glass-run channel, a retainer portion for retaining a weather strip, a flange portion that connects the retainer portion and the groove portion and partially forms an outer surface of a door of a vehicle, and a sash molding configured to cover the flange portion. The flange portion has a first configuration in which the flange portion is not covered by the sash molding and a second configuration in which the flange portion is covered and compressed by the sash molding.

Abstract: In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

Abstract: A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS·FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.

Abstract: Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

Abstract: A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

Abstract: An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.

Abstract: A center-channel protector for a vehicle sash door is arranged between a main sash and a center channel. A body of the protector has an H-shaped upper-end surface which is compatible to cover the upper end of the center channel. The body integrally includes a pair of branch covering portions corresponding to a pair of branch portions constituting the center channel and a middle covering portion disposed between the branch covering portions so as to connect the both branch covering portions therewith. An engaging portion is provided with the body and is mechanically engaged, in a direction intersecting a vertical direction, with an engaged portion which is provided with a center channel side. In collaboration with the engaged portion, the engaging portion constitutes a fastening mechanism by which the protector is fastened on the center channel.

Abstract: A resistor R1 formed by forming a first resistor layer 5a of 20 nm thickness including a tantalum nitride film at a concentration of nitrogen of less than 30 at % and a second resistor layer of 5 nm thickness including a tantalum nitride film at a concentration of nitrogen of 30 at % or more successively by a reactive DC sputtering method using tantalum as a sputtering target material and using a gas mixture of argon and nitrogen as a sputtering gas, and then fabricating the first and the second resistor layers, in which the resistance change ratio of the resistor can be suppressed to less than 1% even when a thermal load is applied in the interconnection step, by the provision of the upper region at a concentration of nitrogen of 30 at % or more.