Abstract: When an instruction decoder decodes an instruction code included in packet data, a copy flag and copy number information are provided to a self-synchronous transfer control circuit. In the self-synchronous transfer control circuit, when a data transfer enabling signal is applied from a C element in a subsequent stage, a node number manipulation circuit manipulates a node number to make copies such that packets can be distinguished from each other, and then data is transferred from a pipeline register to a pipeline register in a subsequent stage.

Abstract: A data-driven type information processing apparatus includes at least a paired data generating unit, a memory control unit, and data memory. The memory control unit includes a pipeline register receiving a data packet output from the paired data generating unit, including a page address, a set value for setting an effective bit and data, and an address generating unit for generating an address for accessing the data memory by retrieving effective data from the data included in the data packet based on the set value and attaching the page address included in the data packet to the retrieved effective data.

Abstract: A data driven type processing device has an error diffusion computing unit built therein. An error holding register is provided within the error diffusion computing unit, and is used to successively store and update a value of error information of a pixel that is to be diffused to a neighboring pixel being processed continuously. An error data memory is provided outside the computing unit, and is used to store and update a value of the error information that is to be diffused to another neighboring pixel being processed discontinuously. The error information and the values to be diffused are stored in a packet, and the packet is circulated for operation.

Abstract: A data packet, having a flag for determination of its processing content, a tag field and a data field, is sequentially transferred between pipeline registers according to pulses from C elements. A determination is made as to whether the tag field of the data packet includes information identical to that pre-stored in a tag field of a register within a processing content determination unit. Based on the determination result, the data packet is processed according to the information stored in a processing content determination field of the register.

Abstract: A branching control unit includes a logic gate and a NAND circuit that can receive transfer permission for each branching designation. The branching control unit further includes a transfer request unit receiving respective outputs of the logic gate and NAND circuit. The transfer request unit sends a data transfer request to a branching designation when the logic gate or NAND circuit is rendered active. Since transfer permission can be received for each branching designation to send a transfer request, a data waiting state depending upon the data holding state of another branching destination will no longer occur. Thus, a data driven type information processing apparatus and method of transferring a data packet at higher speed in a data transmission path can be provided.

Abstract: A data-driven type information processor includes a function processor manipulating contents in a data packet, a program storage unit storing a data flow program used by the function processor, and a branch unit controlling data flow whether to allow flow of a data packet within the processor or to provide the data packet to the outside thereof. An instruction code to provide the data packet storing a result of an operation being performed in the data-driven type information processor being executing the data flow program through the branch unit to the outside of the processor while holding the result of operation is prepared. Then, the instruction code is described in a desired portion in the data flow program. The function processor also attains an operation function to execute the instruction code.

Abstract: A data transmission line used connected continuously in a plurality of stages in an asynchronous system includes a transfer control circuit, synchronous and asynchronous data holding circuits and a timing adjustment circuit. The data transmission line receives and holds data transmitted from a data transmission line of a preceding stage or data output from an external clock synchronous circuit, and outputs and transmits the data to a data transmission line of a succeeding stage. Timing adjustment circuit adjusts data input timing by the transfer control circuit to the synchronous and asynchronous data holding circuits so that data can surely be taken in. It becomes possible to surely take in and transmit data output from external synchronous system in an asynchronous data transmission line at a desired arbitrary timing.

Abstract: A router is formed by an M-input, 1-output junction unit and a 1-input, N-output branching unit. Where M and N satisfy the relation of (M>N), the transfer rate of a path between the junction unit and the branching unit is made the total sum of the transfer rates of inputs of IN1 to INM, whereby N times faster transfer becomes possible.

Abstract: A self-synchronous FIFO memory device (100) has a structure in which n self-synchronous data transmission lines (111-11n) are arrayed in parallel. An input control section (101) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a first transfer request signal, a first acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a preceding-stage section. Further, an output control section (102) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a second transfer request signal, a second acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a succeeding-stage section.

Abstract: A data driven information processor receives a data packet including at least destination information, instruction information, and one or more data, executes a process according to a data flow program prestored in a program storage unit, and stores the processed result in the received data packet for output of the data packet. In the process, a transfer process of a plurality of data between a data memory and a data packet is performed. In this data transfer process, a plurality of addresses not continuous in the data memory are specified by addressing based on the contents of the data packet. The plurality of data read out from the specified addresses are stored in the data packet. Also, the plurality of data in the data packet are respectively written into a plurality of specified addresses not continuous.

Abstract: An address calculation unit calculates a plurality of addresses corresponding to a plurality of data included in a data packet. A first bank memory access unit accesses a first bank memory according to a first address calculated by the address calculation unit. Simultaneously, a second bank memory access unit accesses a second bank memory according to a second address calculated by the address calculation unit. A packet reconstruction unit reconstructs the data packet according to the results of access by the first and second bank memory access units. Accordingly the processing rate of the data packet including a plurality of data is increased.

Abstract: A data-driven type information processing apparatus includes at least a paired data generating unit, a memory control unit, and data memory. The memory control unit includes a pipeline register receiving a data packet output from the paired data generating unit, including a page address, a set value for setting an effective bit and data, and an address generating unit for generating an address for accessing the data memory by retrieving effective data from the data included in the data packet based on the set value and attaching the page address included in the data packet to the retrieved effective data.

Abstract: When the cache memory unit reads the last word of a page of the cache memory, the external memory interface reads ahead data of a prescribed number of pages ahead of the relevant page. Thus, data corresponding to the access request to the external main memory is always held in the cache memory. This prevents degradation of parallel processing capability of the data driven type information processing apparatus.

Abstract: In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other packet flow, a self-synchronous transfer control circuit having a function of controlling transfer operation is used, by which the number of packet copies output from a data holding register is managed by a counter, and the number of copies represented by the copy request packet and the counter count value are compared by a comparator, to determine completion of the packet copying operation.

Abstract: A video signal processor includes a receiver unit receiving a broadcasted wave, an identify unit identifying a broadcasting system according to a signal received by the receiver unit, and a plurality of data driven processors processing a video signal received by the receiver unit according to the broadcasting system identified by the identify unit. Since the plurality of data driven processors process a video signal received by the receiver unit according to the broadcasting system identified by the identify unit, video data corresponding to the broadcasting system can be generated.

Abstract: The data driven type information processing system has a branch unit and a junction unit in the input and output stages thereof, and includes a plurality of data driven type processors between the branch unit and the junction unit. The branch unit, the junction unit and the plurality of data driven type processors are coupled to one another via transmission paths. Each of the data driven type processors can process a unique instruction system. The junction unit collects data packets provided via the transmission paths and outputs the collected data packets to the outside of the system. In operation, when a data packet is provided to the system, the branch unit receives the data packet provided thereto and, according to an instruction code within the received data packet, selects a transmission path connected to a data driven type processor that can process an instruction system corresponding to the instruction code, and sends out the received data packet to the selected transmission path.

Abstract: A video signal processor includes a receiver unit receiving a broadcasted wave, an identify unit identifying a broadcasting system according to a signal received by the receiver unit, and a plurality of data driven processors processing a video signal received by the receiver unit according to the broadcasting system identified by the identify unit. Since the plurality of data driven processors process a video signal received by the receiver unit according to the broadcasting system identified by the identify unit, video data corresponding to the broadcasting system can be generated.

Abstract: An input port receives input data X, generates input packets by adding generation numbers and node numbers indicative of prescribed destinations, in the order of reception, and in addition, generates a data packet from a separately input clock signal. The input data packet is written to an image memory using the generation number in the packet as an address signal, or read from the image memory using the generation number in the data packet as an address signal. Operation is performed in accordance with the input data packet or the data packet read from the image memory by a memory interface, and the processed data packet is output to the outside of a data driven engine, a memory interface or a data driven type processor.

Abstract: A data driven type processing device has an error diffusion computing unit built therein. An error holding register is provided within the error diffusion computing unit, and is used to successively store and update a value of error information of a pixel that is to be diffused to a neighboring pixel being processed continuously. An error data memory is provided outside the computing unit, and is used to store and update a value of the error information that is to be diffused to another neighboring pixel being processed discontinuously. The error information and the values to be diffused are stored in a packet, and the packet is circulated for operation.

Abstract: A router is formed by an M-input, 1-output junction unit and a 1-input, N-output branching unit. Where M and N satisfy the relation of (M>N), the transfer rate of a path between the junction unit and the branching unit is made the total sum of the transfer rates of inputs of IN1 to INM, whereby N times faster transfer becomes possible.