Abstract: A data driven type information processor includes a data driven type information processing unit, and a download unit. The information processing unit includes a program storing unit and an input/output control unit of a data packet for storing information stored in a data packet including a load instruction into the program storing unit and for carrying out a data driven type process on data packets including other instructions according to information stored in the program storing unit. The download unit downloads program data to the information processing unit by applying a data packet including the load instruction and program data to be stored in the program storing unit.

Abstract: A data driven type information processor includes a firing control unit, an operation unit, and a program storage unit. Each of these units has a function of initializing itself in response to an initialization data packet in a specific form.

Abstract: A data-driven information processing device includes a program storage mechanism, a data pair generation mechanism, an operation processing mechanism, a circular pipeline for data transfer among the program storage mechanism, the pair data generation mechanism and the operation processing mechanism in a token format, and a data input/output control circuit connected to the circular pipeline. The data pair generation mechanism carries out a generation process of a data pair in a different manner depending upon whether the argument data companion to the argument data in an applied token is a constant or not. The data pair generation mechanism may include, for example, a constant data processing unit and a dynamic data pair generation mechanism.

Abstract: A method and device for configuring data packets for a data driven processor, the data driven information processor having a data packet producing device that produces the data packets, and a data flow ring architecture for operating (according to data flow computational protocol) upon data packets received from the data packet producing device. The data packet producing device configures each data packet to include a multidimensional generation number. The multidimensional generation number has at least two components, enabling it to identify at least two things to the data flow ring architecture. The first component identifies a generation to which data contained in the data packet belongs. The second component identifies an additional attribute of the data contained in the data packet.

Abstract: A data driven processor includes an H register storing output destination information in path connection verification, and a circuit for selectively providing a data packet to one of a plurality of output ports according to a path verification flag and destination information included in an input data packet and the contents of the H register. The processor 250 may further include a circuit for applying a data packet to an image memory unit according to a path verification flag included in the input data packet and the contents of the H register, and a circuit for directly providing to the output processing unit a data packet for testing returned from an image memory unit according to the path verification flag thereof. A data driven information processing device including a plurality of data driven processors and a method of verifying a path connection in this data driven information processing device are also disclosed.

Abstract: A data flow information processing apparatus includes one or a plurality of data driven type processors for processing data packets based on a data flow program, one or a plurality of memories accessed by these processors, and a router receiving data packets processed by these data processors for selecting a path for selectively applying the data packet to any of the one or the plurality of memories. More preferably, a first router includes an address calculating unit for calculating the address based on the content of the data packet, and a branching unit for branching the path of the data packet based on the calculated address. The data packet includes a generation number allotted in accordance with the order of input time and data. The address calculating unit includes a unit for calculating a modified address by modifying the generation number based on the data.

Abstract: A data driven type information processor includes a control unit having a function of storing a data flow program and accessing it, and a function of producing an operand data pair, the control unit further including one memory shared by both functions. When a program is executed, program data per 1 accessing to the memory and operand data related to the program data are read out simultaneously and applied to an operation unit. Accordingly, a program memory and a memory for queuing operand data, which, were separately provided in a conventional technique, are combined into a single mechanism. Thereby, the number of stages of processing in program execution in the information processor is reduced and increase in program execution speed is permitted.

Abstract: A memory interface device capable of memory accessing suitable for video image signal processing and memory accessing designating an arbitrary address. The interface includes an input scrambler for rewriting the generation number of an input data packet utilizing first data and/or second data when the instruction code of the input data packet is a table conversion instruction, and otherwise outputting the input data packet as it is, and a memory accessing circuit accessing an image memory using the generation number of the applied input data packet as an address and outputting the result of accessing. The device produces and outputs an output data packet from the result of accessing output from the memory accessing circuit and the input data packet.

Abstract: An interface device includes a data transmitter provided with a multiplexer for dividing k.times.n bits of data (k is an integer satisfying k.gtoreq.2) applied from a transmitting side data terminal equipment into k groups for time sequential output, and a data receiver provided with a data latch circuit for taking the first k-1 data groups transmitted from the data transmitter and a data latch circuit for taking the outputs from the k-1 data latch circuits and the last transmitted data group. In a period corresponding to one transmission, two data groups are supplied in time sequence from the data transmitter to the data receiver. There may be provided k data latch circuits so that the inputs of data latch circuit are all passed through the data latch circuits.

Abstract: A data processing system includes a data driven processor for carrying out a plurality of different information processing in parallel using respective plurality of provided data packets, a router, and a plurality of von Neumann processors. When a von Neumann processor provides program data packets to the data driven processor via the router to carry out program loading in the data driven processor, another von Neumann processor provides to the data driven processor a data packet storing dumping information via the router. The data driven processor dumps and provides a loaded program data according to the dumping instruction of the provided packet. Therefore, a plurality of von Neumann processors can be connected on-line to at least one data driven processor to carry out in parallel a plurality of different types of data transfer between the data driven processor and each von Neumann processor.

Abstract: A plurality of self-synchronous type transfer control circuits and data hold circuits are provided corresponding to a plurality of flow paths. A transfer control circuit for controlling flag transfer and a flag holding circuit for holding a flag are provided. A decoder applies a transfer acknowledging signal for permission of transfer to one of the plurality of transfer control circuits according to a flag held by the flag holding circuit. A data selector outputs data provided from a data holding circuit to a data holding circuit in a succeeding stage according to the flag held by the flag holding circuit.

Abstract: A memory interface apparatus includes: a pipeline register holding a data packet from a transmission path to provide an instruction code, a generation number, and data separately; a memory access unit accessing an image memory according to the instruction code, a circuit latching the output of the image memory; an ALU carrying out an operation specified by the instruction code from the pipeline register between data from the pipeline register and the output of the latch circuit for output of the operation result; a selector responsive to a select signal for selecting one of data from the pipeline register and the output of the ALU to apply the selected result to the image memory as data; an output unit generating a data packet including a result of a series of complex operation carried out by the pipeline register, the image memory, and the ALU for output; a transmission control unit controlling transmission of a data packet on the transmission path carried out by the pipeline register and the output unit; an

Abstract: A system having multiple data flow processors is provided which can independently test the operation of each individual data flow processor so that any failure found in the test will easily be located. A host computer is selectively connected to one of a plurality of data flow processors through a switching unit. The switching unit can select one of the data flow processors which can independently be tested.

Abstract: In a data driven information processing system including processors which processes datapackets, a method of verifying identification information allocated to the processors includes the following steps: previously specifying a path for a datapacket via the processors; providing the data driven information processing system with information specifying the number of the other processors for the datapacket to pass through until the packet reaches a certain processor from the input of the system in the path, and a datapacket for identification which stores an identification data verification instruction; a first transmission step of transmitting the datapacket for identification to the processor along the specified path while updating information indicating the number of processors and applying the packet to the processor; a step of producing a result datapacket which stores the identification data of the processor for output in the specified path; a second transmission step of transmitting the result datapacket

Abstract: A data driven type information processing apparatus includes an information processing unit for carrying out an operation process according to a data flow program based on a data packet with a tag attached thereto, and a tag attaching unit provided in an input stage of the information processing unit. The tag attaching unit attaches a prescribed tag to data without a tag, which is applied externally or from another information processing apparatus connected on-line to generate a tagged data packet, and applies the tagged packet to the information processing unit. An information processing apparatus which is connected on-line to the present information processing apparatus and mutually exchanges the processed data mutually is not limited to either von Neumann type or non Neumann type (data driven type).

Abstract: A self-timed clocking transfer control circuit includes a flipflop for storing a transition of a transfer request signal to an L level and outputting an H level signal, an inverter for applying a transfer acknowledge signal to a preceding stage, a 5-input NAND gate, and a second signal output circuit for applying a transfer request signal to a succeeding stage in response to a transition of the output of the 5-input NAND gate to the L level. The 5-input NAND gate does not output the L level unless the transfer request signal from the preceding stage, the output of the flipflop, the transfer acknowledge signal from the succeeding stage, the transfer request signal output by the self-timed clocking transfer control circuit itself, and the prohibition signal are all in the H level. Setting the prohibition signal to the L level, self-synchronous type transfer control can be prohibited.

Abstract: A data transmission apparatus includes one input-side transmission path and a plurality of output-side transmission paths. The input-side transmission path includes a plurality of handshaking-type data transmission paths provided in series. Each of the output-side transmission paths includes a plurality of handshaking-type data transmission paths provided in series. Data to be transmitted includes an identifier for designation any or all of the plurality of output-side transmission paths. A comparison and determination logic portion determines whether the identifier included in the data designates any of the plurality of output-side transmission paths or all of them. A control portion sends the data supplied from the input-side transmission path to any or all of the plurality of output-side transmission paths, in response to a signal outputted from the comparison and determination logic portion.

Abstract: A refresh control circuit includes a refresh request generating circuit, a multiplexer, a memory access control circuit and an elimination control circuit. The refresh request generating circuit periodically outputs a transfer pulse and a refresh packet for refreshing. The merging control circuit receives a transfer pulse for normal access and a transfer pulse for refreshing. The merging control circuit, when the transfer pulse for refreshing and the transfer pulse for normal access contend with each other, applies first the transfer pulse to the memory access control circuit, makes the other stand by and generates an identification signal for identifying normal access and refreshing. The multiplexer receives a refresh packet and a data packet and applies one of the packets to the memory access control circuit in response to the identification signal.

Abstract: A data sizing circuit in a data flow type system is disclosed. A copy is made of the data included in a packet. The original first data of M.times.N bits is circulated by N-bit unit, where only the required bits are selectively written into the memory and read out. M (M is integer) is added to the address corresponding to the copied second data, and data of M.times.N bits is circulated by N-bit unit, where only the required bits are selectively written into the memory and read out. The first and second data read out from the memory are synthesized, circulated by N-bit unit, and output. Data of plural types with different data width can be read/written into an arbitrary address without wasting memory.

Abstract: A conveyor mechanism for transferring cylindrical articles, such as, cigarettes embodies a single belt conveyor which does the conveying from a lower level to a higher level. The surface used for conveyance has a curved portion unlike belt conveyors in general use and a plurality of pins project from at least one side of the belt in parallel relation to each other. At the curved section, these pins are held by a suitable means such that the belt maintains the curvature. Cigarettes or other cylindrical objects are fed by the internal surface of the curving belt and an auxiliary belt conveyor.