Abstract: An image operation processing apparatus is connected to a memory. The apparatus processes, by accessing the memory, a data packet including instruction information and an address of a prescribed address space. The apparatus realizes an address translation process for translating the address included in an incoming data packet to an address of a partial address space smaller than the prescribed address space. It further realizes a memory access process for accessing the memory in accordance with the address translated by the address translation process. Finally, it performs a process in accordance with the instruction information included in the data packet.

Abstract: A C element controls a pipeline register and successively transfers data packets. When a dead-lock state occurs, a data packet in the pipeline register is erased by a master reset signal, a host transfer flag operating circuit overwrites a data packet in the pipeline register so that it has a host transfer flag at the “H” level, and thereafter, when the host transfer flag is detected in the subsequent stage, the data packet is transferred to the host.

Abstract: When an instruction decoder decodes an instruction code included in packet data, a copy flag and copy number information are provided to a self-synchronous transfer control circuit. In the self-synchronous transfer control circuit, when a data transfer enabling signal is applied from a C element in a subsequent stage, a node number manipulation circuit manipulates a node number to make copies such that packets can be distinguished from each other, and then data is transferred from a pipeline register to a pipeline register in a subsequent stage.

Abstract: An input port receives input data X, generates input packets by adding generation numbers and node numbers indicative of prescribed destinations, in the order of reception, and in addition, generates a data packet from a separately input clock signal. The input data packet is written to an image memory using the generation number in the packet as an address signal, or read from the image memory using the generation number in the data packet as an address signal. Operation is performed in accordance with the input data packet or the data packet read from the image memory by a memory interface, and the processed data packet is output to the outside of a data driven engine, a memory interface or a data driven type processor.

Abstract: A data packet, having a flag for determination of its processing content, a tag field and a data field, is sequentially transferred between pipeline registers according to pulses from C elements. A determination is made as to whether the tag field of the data packet includes information identical to that pre-stored in a tag field of a register within a processing content determination unit. Based on the determination result, the data packet is processed according to the information stored in a processing content determination field of the register.

Abstract: An arithmetic logic unit capable of executing an instruction belonging to a user-defined instruction area at the same clock frequency as a hard-wired logic includes a memory storing data at an arbitrary address and outputting the data stored in the address when an instruction code and an operand data are applied as an address. When an instruction decoder decoding part of the instruction code for setting the memory to read mode or write mode is provided, contents of the memory can be re-written, and therefore the content of the memory can be readily changed even after delivery. The arithmetic logic unit may include, in place of the memory, a programmable logic device adapted to receive an instruction code and the operand data and capable of organizing a desired logic.

Abstract: A data driven information processor includes an operation processor unit for prestoring a data flow program and carrying out processing, and a storage microprocessor unit having a plurality of data memories including external data memories for inputting/outputting data to and from the operation processor unit. In the storage microprocessor unit, a plurality of data memories are accessed, in parallel, based on the content of an applied data packet for a single access time. The result of each access is operated in accordance with the content of the data packet. Finally, the subsequent program is read from a data flow program prestored in the storage microprocessor unit so that access to the plurality of data memories and processing of a result of the access continue in the storage microprocessor unit. Thus, in the information processor, parallel access to a plurality of data memories can be achieved by program control independent of program control by the operation processor unit.

Abstract: A data flow information processing apparatus includes one or a plurality of data driven type processors for processing data packets based on a data flow program, one or a plurality of memories accessed by these processors, and a router receiving data packets processed by these data processors for selecting a path for selectively applying the data packet to any of the one or the plurality of memories. More preferably, a first router includes an address calculating unit for calculating the address based on the content of the data packet, and a branching unit for branching the path of the data packet based on the calculated address. The data packet includes a generation number allotted in accordance with the order of input time and data. The address calculating unit includes a unit for calculating a modified address by modifying the generation number based on the data.

Abstract: A data driven information processor includes a main body processing portion for processing a data packet, a start register storing information for use in determining whether to continue to process the data packet output from the main body processing portion or output externally, and a branch portion for determining whether to provide the output of the main body processing portion to the main body processing portion or to the output processing portion based on the content of the register and the content of the data packet and branching the data packet. The branch portion has a duplicating function to produce a duplicate of the data packet for provision to the output processing portion if it determines the data packet should continue to be processed by the main body processing portion.

Abstract: A data driven information processor includes an input control portion for producing a first data packet including common identification information and a plurality of pieces of data, a junction portion for controlling input of the first data packet and a second data packet, a firing control portion for detecting data to be paired with data in the selected data packet and outputting paired data, an operation processing portion for operating the paired data, a program storage portion for producing and outputting a second data packet based on a result of operation, and a branching portion for controlling whether to output the second data packet to the junction portion or to another data driven information processor. A plurality of such data driven information processors are connected for parallel processing.

Abstract: A data driven type information processor includes a firing control unit, an operation unit, and a program storage unit. The firing control unit sequentially receives data packets, and detects a data packet which stores paired data, and outputs the detected data packet. The operation unit receives a data packet output from the firing control unit, operates on the contents of the received data packet, stores the operation result in the received data packet, and outputs the received data packet. The program storage unit receives the data packet output from the operation unit, and reads a program word formed of a plurality of program word sets from a prestored data flow program by addressing based on the contents of the received data packet.

Abstract: A memory interface apparatus includes a plurality of data memories MEMs, and address modification units AMDs and memory access units I/Fs respectively corresponding to the plurality of data memories MEMs. Each address modification unit AMD has an offset table OFT for pre-storing a plurality of offsets, reads an offset from the table OFT based on received second data D2, modifies an address indicated by a received generation number GN using the read offset, and applies a resultant address to a corresponding memory access unit I/F. Each memory access unit I/F accesses a memory MEM based on the applied address, according to a received operation code C. Each result of access is applied in parallel to an operation unit ALU, which in turn performs operation of the applied result according to an operation code C. Thus, operation processing which compounds access to a memory can be carried out, utilizing parallelism in processing sufficiently.

Abstract: In a system in which a plurality of data driven information processors are connected to each other to receive a data packet and to carry out processing simultaneously, each processor stores a processor number parameter ID of a data packet to be forcibly included in a specific data packet to be input. The forced input packet is a packet which each processor should receive and process unconditionally among packets addressed to the other processors excluding itself. The parameter ID is a number for identifying the other processors. Upon reception of an ordinary data packet, the processor compares information for specifying a processor to process the received ordinary data packet respectively with parameter ID and processor identification number PE# preassigned to each processor for identifying itself, and in response to matching between the information and any one of parameter ID and processor identification number PE#, takes in the received ordinary data packet in order to process the same.

Abstract: A data processing apparatus which can carry out an accumulation operation spanning a plurality of packets within the same generation at high speed without increasing hardware cost includes an internal circular path for circulating an extended packet provided with an accumulated value field ACC, an operation unit, an arithmetic circuit, an adder, and a shifter. The operation unit adds an input data and a value of ACC according to an instruction code using the arithmetic circuit, the adder, and the shifter, and updates a data field of an output packet or the ACC field. The contents of the data field and the ACC field can be varied by changing the way of selecting in a selector. A packet without the ACC field is utilized for external input/output, so that the apparatus converts the form of the packet upon input/output.

Abstract: A method and device for configuring data packets for a data driven processor, the data driven information processor having a data packet generator that generates the data packets, and a data flow ring architecture for operating (according to data flow computational protocol) upon data packets received from the data packet generator. The data packet generator configures each data packet to include a multi-attribute tag. The multi-attribute tag has a first component and a second component. The first component identifies one of a plurality of data sets to which data contained in the data packet belongs. The second component uniquely identifies the data within the particular data set identified by the first component contained in the data packet. Where the data driven information processor is doing image processing: the first component of the multi-attribute tag is the field/image number; and the second component of the multi-attribute tag is the location of a pixel in the field/image.

Abstract: A data transfer control unit for controlling data transfer between a main processing part executing information processing and a memory part accessed by the main processing part has a bit width control part for controlling the bit width of the transferred data so that a first bit width of a port for data input/output on the main processing part side is matched with a second bit width, which is narrower than the first bit width, of a port for data input/output on the memory part side. This bit width control part has a function of converting the bit width of the data to the second bit width in case of data transfer from the main processing part to the memory part and a function of converting the same to the first bit width in case of data transfer from the memory part to the main processing part. Thus, the capacity of the memory part can be reduced by adjusting the bit width of the data transferred between the main processing part and the memory part.

Abstract: A data driven information processor capable of readily performing appropriate processing to input data according to their meanings includes a data packet forming portion forming a data packet having a tag including a generation number, a destination number, instruction information and a constant value based on externally input data. The data packet forming portion includes a generation number generation processing portion for generating a multi-dimensional generation number to be added to input data based on an order of the data and a destination number generation processing portion for generating a tag as a function of a generation number generated by the generation number generation processing portion. One of a generation number operation processing portion performing operation for each dimension of a generation number and a copy processing portion copying a portion of a generation number into a destination number, or both of these processing portions, may also be provided.

Abstract: A data driven processor includes an output processing unit outputting a data packet outside the processor while referencing a branch control parameter register group. In the register group, a processor number/generation number specifying parameter P/G, a branch comparison parameter RM, and a branch comparison data parameter RD are stored. At the time of output of the data packet, the output processing unit reads out any one of a processor number and a generation number in the data packet according to parameter P/G, and sends out the data packet to any one of output ports OA and OB according to the result of predetermined operation processing using the read out number and parameters RM and RD. When a plurality of processors which operate as described above are connected to each other to carry out processing simultaneously while inputting/outputting a data packet, a data path among the processors can be set and changed easily according to any of the processor number and the generation number in the packet.

Abstract: A data driven type information processing apparatus includes a generation number translation table and a generation number translation circuit. The generation number translation table includes translated generation numbers. The translated generation numbers have been calculated in advance in relation to the generation numbers by a prescribed functional relation. An address of the translated generation number is specified by a prescribed calculation on the generation number. In response to a generation number translation instruction, the generation number translation circuit accesses the generation number translation table based on the content of the generation number field of the applied data packet, and reads the corresponding translated generation number. Further, the generation number translation circuit rewrites the generation number of the applied data packet with the read translated generation number.

Abstract: Function processor FP of a data driven type information processor includes mechanism A receiving plural field generation number GN (representing pixel coordinate information), instruction code OPC, and condition X determining a divisional configuration of the generation number. Mechanism A takes out a bit field designated by instruction code OPC and/or the condition from applied generation number GN. Data of the taken out bit field is sent to arithmetic and logic unit A. Arithmetic and logic unit A carries out operation between data of the bit field and right data R-DATA. The operation result is sent to mechanism B. Mechanism B receives instruction code OPC, generation number GN, and condition X determining a divisional configuration of the generation number. The above described operation result is stored in the bit field of generation number GN designated by instruction code OPC and/or condition X.