Patents by Inventor Tue Nguyen
Tue Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6015918Abstract: A Cu(hfac) allyl-derived ligand precursor has been provided. The ligand includes group consisting of alkyl, phenyl, trialkylsilane, trialkoxylsilane, halodialkylsilane, dihaloalkylsilane, trihalosilane, triphenylsilane, alkoxyl, halogen, chloroformate, cynanide, cycloalkyl, cycloalkylamine, alkyl ether, isocyanate, and pentafluorobenzene. Examples of the allyl-derived ligand precursors have proved to be stable at room temperatures, and sufficiently volatile at higher temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described precursors, including a Cu(hfac)(allyltrimethylsilane) precursor.Type: GrantFiled: March 30, 1999Date of Patent: January 18, 2000Assignee: Sharp Laboratories of America, Inc.Inventors: Wei-Wei Zhuang, Tue Nguyen, Greg Michael Stecker, David Russell Evans, Sheng Teng Hsu
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Patent number: 6002176Abstract: A method for selectively applying CVD copper to metallic surfaces, that are co-located with non-metallic surfaces, is provided. The method prepares both the metal and non-metallic surfaces with a low energy ion etch of an inert gas. The etching promotes the growth of copper on the metallic surface, and inhibits the growth on the non-metallic surface. Following an application of CVD copper, the surfaces are etched again to clean any residual copper from the non-metallic surface, and to again prepare the surfaces for another deposition of copper. Through repeated cycles of etching and copper deposition, the copper overlying the metallic surface is accumulated to achieve the desired thickness, while the non-metallic surface remains free of copper. A method is also provided for the selective deposition of copper on metallic surfaces to fill interconnects in damascene IC structures.Type: GrantFiled: August 17, 1998Date of Patent: December 14, 1999Assignees: Sharp Laboratories of America, Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Lawrence J. Charneski, Sheng Teng Hsu
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Patent number: 5994571Abstract: A Cu(hfac) precursor with a substituted ethylene ligand has been provided. The substituted ethylene ligand includes bonds to molecules selected from the group consisting of C.sub.1 to C.sub.8 alkyl, C.sub.1 to C.sub.8 haloalkyl, H, and C.sub.1 to C.sub.8 alkoxyl. One variation, the 2-methyl-1-butene ligand precursor has proved to be stable at room temperature, and extremely volatile at higher temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. Because of the volatility, the deposition rate of copper deposited with this precursor is very high. A synthesis method has been provided which produces a high yield of the above-described precursor.Type: GrantFiled: December 18, 1998Date of Patent: November 30, 1999Assignee: Sharp Laboratories of America, Inc.Inventors: Wei-Wei Zhuang, Tue Nguyen, Lawrence J. Charneski, David Russell Evans, Sheng Teng Hsu
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Patent number: 5948467Abstract: A method of enhancing copper adhesion to a substrate includes preparing a single-crystal silicon substrate; forming integrated circuit components on active areas of the substrate; metallizing the integrated circuit components, including metallizing a first copper layer by low-rate CVD, and metallizing a second copper layer by high-rate CVD; and finalizing construction of the structure.Type: GrantFiled: July 24, 1998Date of Patent: September 7, 1999Assignees: Sharp Laboratories of America, Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Lawrence J. Charneski, Masato Kobayashi
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Patent number: 5939334Abstract: A system and method of selectively etching copper surfaces free of copper oxides in preparation for the deposition of an interconnecting metallic material is provided. The method removes metal oxides with .beta.-diketones, such as Hhfac. The Hhfac is delivered into the system in vapor form, and reacts almost exclusively to copper oxides. The by-products of the cleaning process are likewise volatile for removal from the system with a vacuum pressure. Since the process is easily adaptable to most IC process systems, it can be conducted in an oxygen-free environment, without the removal of the IC from the process chamber. The in-situ cleaning process permits a minimum amount of copper oxide to reform before the deposition of the overlying interconnection metal. In this manner, a highly conductive electrical interconnection between the copper surface and the interconnecting metal material is formed.Type: GrantFiled: May 22, 1997Date of Patent: August 17, 1999Assignees: Sharp Laboratories of America, Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Lawrence J. Charneski, David R. Evans, Sheng Teng Hsu
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Patent number: 5936707Abstract: A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.Type: GrantFiled: January 16, 1998Date of Patent: August 10, 1999Assignees: Sharp Laboratories of America, Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Bruce Dale Ulrich, David Russell Evans
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Patent number: 5918150Abstract: A method for etching a metallic surface on an integrated circuit (IC) is provided to minimize electrical resistance between the metallic surface and subsequently applied chemical vapor deposition (CVD) copper. The metallic surface is etched with the ions of an inert gas, such as Ar, at low energy levels. A low energy level minimizes the penetration of ions into the metallic surface, and the use of an inert gas minimizes chemical interactions between the metallic surface and the ions. CVD copper is then applied to the etched surface. In one embodiment, an inert gas and oxygen ions are used to prepare the metallic surface. The inert gas ions are used to etch the metallic surface to improve conductivity, and the oxygen ions promote the formation of an oxide layer to improve adhesion between the metallic surface and the copper. An IC comprising a copper stud to interconnect dielectric interlevels with improved electrical conductivity is also provided.Type: GrantFiled: October 11, 1996Date of Patent: June 29, 1999Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Jer-Shen Maa
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Patent number: 5914202Abstract: A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity of phase shifted light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.Type: GrantFiled: June 10, 1996Date of Patent: June 22, 1999Assignees: Sharp Microeletronics Technology, Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Bruce Dale Ulrich, David Russell Evans
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Patent number: 5913144Abstract: A method has been provided for improving the adhesion of Cu to a diffusion barrier material, such as TiN, in an integrated circuit substrate. The diffusion barrier is exposed to either a reactive oxygen species, or a plasma containing oxygen. A thin layer of the diffusion barrier is oxidized, typically less than 50 .ANG., in response to exposure to the oxygen environment. CVD copper is then deposited over the oxidized diffusion barrier surface. The oxide layer improves bonding between the copper and diffusion barrier surfaces. The oxide layer permits the control of tolerances in the diffusion barrier preparation processes, and copper precursor, to be relaxed. An integrated circuit comprising an oxide layer between the diffusion barrier and the copper layer is also provided.Type: GrantFiled: September 20, 1996Date of Patent: June 15, 1999Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Lawrence J. Charneski, Lynn R. Allen
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Patent number: 5909637Abstract: A method has been provided for improving the adhesion of Cu to a diffusion barrier material, such as TiN, in an integrated circuit substrate. The diffusion barrier material is exposed to either a reactive gas species, or a plasma containing a reactive gas. By removing contaminants on the surface of the diffusion barrier, and forming weak molecular bonds between the diffusion barrier surface and the reactive gas, the diffusion barrier surface is protected and prepared for Cu adhesion. Cu, breaking the bonds between the reactive gas and diffusion barrier surface, readily bonds to the diffusion material for improved adhesion between surfaces. The diffusion barrier surface, prepared with the reactive gas, allows the IC to be stored, delaying the Cu deposition to more convenient times in the IC fabrication process. An Cu conductor interface adhered to the diffusion barrier of an integrated circuit is also provided.Type: GrantFiled: September 20, 1996Date of Patent: June 1, 1999Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki KaishaInventors: Lawrence J. Charneski, Tue Nguyen
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Patent number: 5906910Abstract: A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.Type: GrantFiled: January 16, 1998Date of Patent: May 25, 1999Assignees: Sharp Kabushiki Kaisha, Sharp Microelectronics Technology, Inc.Inventors: Tue Nguyen, Bruce Dale Ulrich, David Russell Evans
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Patent number: 5904565Abstract: A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level.Type: GrantFiled: July 17, 1997Date of Patent: May 18, 1999Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Sheng Teng Hsu
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Patent number: 5900290Abstract: The invention provides a process for depositing fluorinated amorphous carbon (a-F:C) films on IC wafers to provide a low-k interconnect dielectric material. The process, carried out in a PECVD chamber, introduces silane gas (SiH.sub.4) into the mixture of C.sub.4 F.sub.8 and CH.sub.4 gases used to deposit a-F:C films. The silane helps to decrease the fluorine etchants in the deposited film, helping to improve the crosslinks in the deposited product. Film produced in accordance with the present invention has both low-k, generally below 2.4, and high thermal stability, generally above 440.degree. C., allowing for higher thermal anneal temperatures.Type: GrantFiled: February 13, 1998Date of Patent: May 4, 1999Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki KaishaInventors: Hongning Yang, Tue Nguyen
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Patent number: 5897379Abstract: A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one embodiment, sensitive areas of the wafer are covered with photoresist, and the wafer perimeter cleared of photoresist, before the acid is applied. In another embodiment, sensitive areas of the wafer are protected with water spray as the copper etchant is applied. In a third embodiment, the nitric acid is applied to clear the wafer perimeter of copper before a chemical mechanical polishing (CMP) is performed on the layer of deposited copper. The excess thickness of copper protects copper interconnection structures from reacting with the copper etchant. All these methods permit copper to be removed at a low enough temperature that copper oxides are not formed. A semiconductor wafer cleaned of copper in accordance with the above-described method, and a system for low temperature copper removal is also provided.Type: GrantFiled: December 19, 1997Date of Patent: April 27, 1999Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki KaishaInventors: Bruce Dale Ulrich, Tue Nguyen, Masato Kobayashi
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Patent number: 5851367Abstract: A method for selectively applying CVD copper to metallic surfaces, that are co-located with non-metallic surfaces, is provided. The method prepares both the metal and non-metallic surfaces with a low energy ion etch of an inert gas through the use of an ion gun. The etching promotes the growth of copper on the metallic surface, and inhibits the growth on the non-metallic surface. Following an application of CVD copper, the surfaces are etched again to clean any residual copper from the non-metallic surface, and to again prepare the surfaces for another deposition of copper. Through repeated cycles of etching and copper deposition, the copper overlying the metallic surface is accumulated to achieve the desired thickness, while the non-metallic surface remains free of copper. A method is also provided for the selective deposition of copper on metallic surfaces to fill interconnects in damascene IC structures.Type: GrantFiled: October 11, 1996Date of Patent: December 22, 1998Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Lawrence J. Charneski, Sheng Teng Hsu
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Patent number: 5821169Abstract: A method is provided for forming intermediate levels in an integrated circuit dielectric during a damascene process using a hard mask layer to transfer the pattern of a photoresist mask having at least one intermediate thickness. The dielectric is covered with a hard mask layer, and the hard mask layer is covered with the photoresist mask. The photoresist mask pattern is transferred into the hard mask pattern so that the hard mask pattern has at least one intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the hard mask pattern. The hard mask pattern is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is etched to a second depth, less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias.Type: GrantFiled: August 5, 1996Date of Patent: October 13, 1998Assignees: Sharp Microelectronics Technology,Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Chien-Hsiung Peng, Bruce Dale Ulrich
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Patent number: 5767301Abstract: A method is provided for applying chemical vapor deposition (CVD) copper (Cu) to integrated circuit substrates using a Cu(hfac)(ligand) precursor with a silylolefin ligand including combinations of C1-C8 alkyl groups with at least one C2-C8 alkyloxy group. The alkyloxy groups include, ethoxy, propoxy, butoxy, pentyloxy, hexyloxy, heptyloxy, octyloxy, and aryloxy, while the alkyl groups include methyl, ethyl, propyl, butyl, pentyl, hexyl, heptyl, octyl, and aryl. The oxygen atoms of the alkyloxy groups, and the long carbon chains of both the alkyl and alkyloxy groups, increase the stability of the precursor by contributing electrons to the Cu(hfac) complex. The improved bond helps insure that the ligand separates from the (hfac)Cu complex at consistent temperatures when Cu is to be deposited. Combinations of alkyloxy and alkyl groups allow the molecular weight of the precursor to be manipulated so that the volatility of the precursor is adjustable for specific process scenarios.Type: GrantFiled: January 21, 1997Date of Patent: June 16, 1998Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki KaishaInventors: Yoshihide Senzaki, Masato Kobayashi, Lawrence J. Charneski, Tue Nguyen
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Patent number: 5744192Abstract: A method of blending water vapor with volatile Cu(hfac)TMVS (copper hexafluoroacetylacetonate trimethylvinylsilane) is provided which improves the deposition rate of Cu, without degrading the resistivity of the Cu deposited upon an integrated circuit surface. The method of the present invention uses a relatively small amount of water vapor, approximately 0.3 to 3% of the total pressure of the system in which chemical vapor deposition (CVD) Cu is applied. The method specifies the flow rates of the liquid precursor, carrier gas, and liquid water. The method also specifies the pressures of the vaporized precursor, vaporized precursor blend including carrier gas and water vapor. In addition, the temperatures of the vaporizers, chamber walls, and IC surfaces are disclosed. A Cu precursor blend is also provided comprising vaporized Cu(hfac)TMVS and water vapor. The ratio of water vapor pressure to vaporized precursor is approximately 0.5 to 5%.Type: GrantFiled: November 8, 1996Date of Patent: April 28, 1998Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki KaishaInventors: Tue Nguyen, Yoshihide Senzaki, Masato Kobayashi, Lawrence J. Charneski, Sheng Teng Hsu
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Patent number: 5468687Abstract: A method for low temperature annealing (oxidation) of high dielectric constant Ta.sub.2 O.sub.5 thin films uses an ozone enhanced plasma. The films produced are especially applicable to 64 and 256 Mbit DRAM applications. The ozone enhanced plasma annealing process for thin film Ta.sub.2 O.sub.5 reduces the processing temperature to 400.degree. C. and achieves comparable film quality, making the Ta.sub.2 O.sub.5 films more suitable for Ultra-Large Scale Integration (ULSI) applications (storage dielectric for 64 and 256 Megabit DRAMs with stack capacitor structures, etc.) or others that require low temperature processing. This low temperature process is extendable to other high dc and piezoelectric thin films which may have many other applications.Type: GrantFiled: July 27, 1994Date of Patent: November 21, 1995Assignee: International Business Machines CorporationInventors: Dan Carl, David M. Dobuzinsky, Son V. Nguyen, Tue Nguyen
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Patent number: 5455204Abstract: The invention provides a continuous rapid thermal process for forming a substantially uniform oxynitride film on fingered three-dimensional silicon structures comprising cleaning of the silicon substrate and growth of silicon oxide in the presence of ozone, nitridation of the silicon oxide layer in the presence of NH.sub.3 and reoxidation of the oxynitride layer in the presence of oxygen.Type: GrantFiled: December 12, 1994Date of Patent: October 3, 1995Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, Son V. Nguyen, Tue Nguyen