Patents by Inventor Tung-Heng Hsieh

Tung-Heng Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160111370
    Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 21, 2016
    Inventors: Tung-Heng HSIEH, Hui-Zhong ZHUANG, Chung-Te LIN, Ting-Wei CHIANG, Sheng-Hsiung WANG, Li-Chun TIEN
  • Publication number: 20160104674
    Abstract: An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.
    Type: Application
    Filed: January 30, 2015
    Publication date: April 14, 2016
    Inventors: Tung-Heng HSIEH, Hui-Zhong ZHUANG, Chung-Te LIN, Ting-Wei CHIANG, Sheng-Hsiung WANG, Li-Chun TIEN
  • Publication number: 20160093603
    Abstract: A method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC) is disclosed. The method includes determining if a first CUT layout pattern and a second CUT layout pattern are in compliance with a predetermined spatial resolution requirement. If the first CUT layout pattern and the second CUT layout pattern are not in compliance with the predetermined spatial resolution requirement, a merged CUT layout pattern is generated based on the first CUT layout pattern, the second CUT layout pattern, and a stitching layout pattern, and a remedial connecting layout pattern is added to a conductive layer layout. The stitching layout pattern corresponds to a carved-out portion of a third gate electrode structure. The remedial connecting layout pattern corresponds to fabricating a conductive feature electrically connecting two portions of the third gate electrode structure that are separated by the corresponding carved-out portion.
    Type: Application
    Filed: September 29, 2014
    Publication date: March 31, 2016
    Inventors: Tung-Heng HSIEH, Hui-Zhong ZHUANG, Chung-Te LIN, Sheng-Hsiung WANG, Ting-Wei CHIANG, Li-Chun TIEN
  • Publication number: 20160078164
    Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Tung-Heng HSIEH, Chung-Te LIN, Sheng-Hsiung WANG, Hui-Zhong ZHUANG, Min-Hsiung CHIANG, Ting-Wei CHIANG, Li-Chun TIEN
  • Publication number: 20160079162
    Abstract: A semiconductor device includes a substrate having an active area, a gate structure over the active area, a lower conductive layer over and electrically coupled to the active area, and an upper conductive layer over and electrically coupled to the lower conductive layer. The lower conductive layer is at least partially co-elevational with the gate structure. The lower conductive layer includes first and second conductive segments spaced from each other. The upper conductive layer includes a third conductive segment overlapping the first and second conductive segments. The third conductive segment is electrically coupled to the first conductive segment, and electrically isolated from the second conductive segment.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Tung-Heng HSIEH, Hui-Zhong ZHUANG, Chung-Te LIN, Sheng-Hsiung WANG, Ting-Wei CHIANG, Li-Chun TIEN, Tsung-Chieh TSAI
  • Publication number: 20160063166
    Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Patent number: 9269833
    Abstract: Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang
  • Publication number: 20150333002
    Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.
    Type: Application
    Filed: July 28, 2015
    Publication date: November 19, 2015
    Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Patent number: 9136168
    Abstract: A method includes placing two conductive lines in a layout. Two cut lines are placed over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Patent number: 9111768
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yu Lu, Shyue-Shyh Lin, Chin-Shan Hou, Kuo-Feng Yu, Tung-Heng Hsieh, Chih-Hung Wang, Jian-Hao Chen
  • Patent number: 9070624
    Abstract: A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: June 30, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Hao Chen, Chia-Yu Lu, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Hsien-Chin Lin, Shyue-Shyh Lin
  • Publication number: 20150140478
    Abstract: Provided is an integrated circuit (IC) testline layout. The layout has a device boundary and a main pattern boundary inside the device boundary. The layout includes at least one main pattern inside the main pattern boundary. The layout further includes a plurality of dummy patterns in a region that is between the main pattern boundary and the device boundary. The plurality of dummy patterns is printable in a photolithography process and is arranged in a ring with a uniform spacing between two adjacent dummy patterns.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Fan Chen, Tung-Heng Hsieh, Chin-Shuan Hou, Yu-Bey Wu
  • Publication number: 20150087143
    Abstract: A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.
    Type: Application
    Filed: December 1, 2014
    Publication date: March 26, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Che
  • Publication number: 20150048457
    Abstract: A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated feature of the second layer mask that is too close to a feature moved to the second layer mask from the gate contact mask, and connecting two split features of a first layer contact mask, the split features corresponding to the elongated feature of the second layer mask.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting, Chun-Yi Lee
  • Publication number: 20150001734
    Abstract: A method includes placing two conductive lines in a layout. Two cut lines are placed over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Publication number: 20150001678
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Inventors: Chia-Yu Lu, Shyue-Shyh Lin, Chin-Shan Hou, Kuo-Feng Yu, Tung-Heng Hsieh, Chih-Hung Wang, Jian-Hao Chen
  • Patent number: 8901627
    Abstract: A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Che
  • Patent number: 8859386
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yu Lu, Jian-Hao Chen, Chih-Hung Wang, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Shyue-Shyh Lin
  • Publication number: 20140138750
    Abstract: A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Che
  • Publication number: 20130328131
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.
    Type: Application
    Filed: June 8, 2012
    Publication date: December 12, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Lu, Jian-Hao Chen, Chih-Hung Wang, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Shyue-Shyh Lin