Abstract: A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.

Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

Abstract: Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.

Abstract: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.

Abstract: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.

Abstract: A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by reacting a metal and the regrown polycrystalline region having the increased grain size.

Abstract: A silicided gate for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate. A first dielectric layer is formed over the gate electrode and the substrate, and a second dielectric layer is formed over the first dielectric layer. The second dielectric layer is etched to form spacers adjacent the gate electrode. A treatment is performed on the first dielectric layer over the gate electrode, wherein the treatment increases the effective etch rate of the first dielectric layer as compared to untreated portions of the first dielectric layer. An etching procedure is then performed to expose the surface of the gate electrode, the etching procedure recessing the liner along sidewalls of the gate electrode. Thereafter, a silicide procedure is performed to silicide at least a portion of the gate electrode.

Abstract: A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by reacting a metal and the regrown polycrystalline region having the increased grain size.