Abstract: A light-emitting diode display device includes a light-emitting diode and a substrate. The light-emitting diode includes a central axis, and the substrate includes a first connecting portion and a second connecting portion. The central axis is extended through the first connecting portion. The second connecting portion is disposed outside of the first connecting portion and is spaced apart from the first connecting portion by a distance which is greater than zero, and the first connecting portion and the second connecting portion are respectively electrically connected to the light-emitting diode.

Abstract: Provided is a display device, which includes a substrate, a transistor, a capacitor and a light emitting unit. The transistor and the capacitor are disposed on the substrate. The light emitting unit is disposed on the substrate and arranged corresponding to the capacitor. The light emitting unit includes a first light emitting diode. The first light emitting diode is electrically connected with the transistor and overlaps the capacitor. The display device has favorable space utilization, provides a repair function, or reduces the probability of failure.

Abstract: Provided is a display device, which includes a substrate, a transistor, a capacitor and a light emitting unit. The transistor and the capacitor are disposed on the substrate. The light emitting unit is disposed on the substrate and arranged corresponding to the capacitor. The light emitting unit includes a first light emitting diode. The first light emitting diode is electrically connected with the transistor and overlaps the capacitor. The display device has favorable space utilization, provides a repair function, or reduces the probability of failure.

Abstract: A ventilation apparatus includes a main body, an air entry and an air exit respectively arranged on two sides of the main body, a filter arranged behind the air entry, and a pressure sensor module located between the filter and the air exit, which senses pressure caused by air flowing inside the main body through the air entry and the filter. The pressure sensor module firstly senses pressure related data when the apparatus begins to start for initial data, and senses pressure related data continuously after the apparatus starts for working data, and transmits these data externally. An analysis monitor device computes a reference pressure offset value and a working pressure offset value according to the initial data and the working data, and compares the two pressure offset values for determining whether the filter needs to be replaced.

Abstract: A display device includes a substrate, a light-emitting element, and a transistor. The substrate has a top surface. The light-emitting element is disposed on the substrate. The transistor is disposed on the substrate, and includes a drain electrode, a gate electrode, and a semiconductor layer. The drain electrode is electrically connected to the light-emitting element. The semiconductor layer includes an overlapping portion overlapped with the gate electrode. The light-emitting element does not overlap with the overlapping portion along a direction perpendicular to the top surface of the substrate.

Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Abstract: Various structures of a semiconductor package assembly are provided. In one implementation, a semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer disposed on the die-attach surface, surrounding the semiconductor die. Further, a first conductive bump disposed over the first solder mask, coupled to a first pad of the redistribution layer (RDL) structure through a single circuit structure on a portion the first solder mask layer, wherein a first distance between a center of the first pad and a sidewall of the semiconductor die, which is close to the first pad, is equal to or greater than a second distance between a center of the first conductive bump and the sidewall of the semiconductor die.

Abstract: An optical detecting apparatus for detecting a degree of freedom error of a spindle and has a standard bar and a sensor module, and is assembled between a spindle and a rotating platform of a powered machinery. The standard bar has a rod lens and a reflection face. The sensor module has two detecting groups, an oblique laser head, and a reflected spot displacement sensor. Each detecting group emits a laser light through the rod lens along the X-axis and the Y-axis of the powered machinery. The oblique laser head emits an oblique laser light to the reflected spot displacement sensor. When the spindle of the powered machinery generates errors after rotating, the sensor module receives the changes of the laser lights to obtain the displacement change signals of the standard bar for a calculation unit to detect the errors between the spindle and the rotating platform.

Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.

Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Abstract: Various structures of a semiconductor package assembly are provided. In one implementation, a semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer disposed on the die-attach surface, surrounding the semiconductor die. Further, a first conductive bump disposed over the first solder mask, coupled to a first pad of the redistribution layer (RDL) structure through a single circuit structure on a portion the first solder mask layer, wherein a first distance between a center of the first pad and a sidewall of the semiconductor die, which is close to the first pad, is equal to or greater than a second distance between a center of the first conductive bump and the sidewall of the semiconductor die.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer is disposed on the die-attach surface. The first solder mask layer surrounds the semiconductor die. An additional circuit structure is disposed on a portion of the first solder mask, surrounding the semiconductor die. The additional circuit structure includes a pad portion having a first width and a via portion has a second width that is less than the first width. The via portion passes through the first solder mask layer to be coupled the redistribution layer (RDL) structure.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die paddle. A supporting bar connects to the die paddle, extending in an outward direction from the die paddle. At least two power leads are separated from the die paddle and the supporting bar, having first terminals close to the die paddle and second terminals extending outward from the die paddle. A power bar connects to the at least two power leads, having a supporting portion. A molding material encapsulates the lead frame leaving the supporting portion exposed.

Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.

Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer is disposed on the die-attach surface. The first solder mask layer surrounds the semiconductor die. An additional circuit structure is disposed on a portion of the first solder mask, surrounding the semiconductor die. The additional circuit structure includes a pad portion having a first width and a via portion has a second width that is less than the first width. The via portion passes through the first solder mask layer to be coupled the redistribution layer (RDL) structure.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die peddle. A supporting bar connects to the die peddle, extending in an outward direction from the die peddle. At least two power leads are separated from the die peddle and the supporting bar, having first terminals close to the die peddle and second terminals extending outward from the die peddle. A power bar connects to the at least two power leads, having a supporting portion. A molding material encapsulates the lead frame leaving the supporting portion exposed.

Abstract: A semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.

Abstract: A method of numerical-control scraping of a work piece has a preparing step, a scanning step, a flatness-parameter inputting step, a surface-finishing step, a related-parameter inputting step, an auto-scraping step and an analyzing step. The preparing step comprises preparing a multi-axis machine tool, a laser displacement meter, an auto scraping apparatus and a computer. The scanning step comprises scanning the work piece. The flatness-parameter inputting step comprises inputting a flatness-parameter. The surface-finishing step comprises calculating out the to-be-scraped ranges of the work piece and scraping the work piece. The related-parameter inputting step comprises inputting desired PPI and POP in the computer, calculating out the HOP, the DOS and the oil content to obtain the length, the width and the depth of a single scraping process. The auto-scraping step comprises scraping the work piece to meet the requirement. The analyzing step comprises detecting the 3D-appearance drawing of the work piece.