Patents by Inventor Tung-Hsien Hsieh

Tung-Hsien Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12158482
    Abstract: A probe card assembly includes a circuit board, a substrate, and at least one passive component. The substrate is disposed opposite and connected to the circuit board. The circuit board has a first opening facing the substrate and/or the substrate has a second opening facing the circuit board. The at least one passive component is disposed between the circuit board and the substrate and is at least partially accommodated in at least one of the first opening and the second opening.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 3, 2024
    Assignee: MEDIATEK INC.
    Inventor: Tung-Hsien Hsieh
  • Publication number: 20240027281
    Abstract: A drive system thermal temperature rise test and compensation system. The system has an optical non-contact type sensing head mounted on a main shaft of a machine tool, and a sensing center is formed in the center of the sensing head. A platform driven by a transmission device of the machine tool is provided with plural ball lens devices, and a temperature sensor for transmitting temperature data externally is further provided on the transmission device. After the machine tool sequentially records an original point coordinate for each ball lens center by using the sensing head, the sensing head is cyclically and sequentially moved to the original point coordinate of each ball lens, so as to measure a displacement error between the sensing center and the ball lens center resulted from thermal shifts of the transmission device, as well as capable of measuring multiaxial errors and using various axial temperatures for compensation.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 25, 2024
    Inventors: Wen-Yuh JYWE, Tung-Hsien HSIEH, Chia-Ming HSU, Yu-Wei CHANG, Sen-Yi HUANG, Ching-Ying CHIU, Pin-Wei LU, Jheng-Jhong ZENG
  • Publication number: 20220196706
    Abstract: A probe card assembly includes a circuit board, a substrate, and at least one passive component. The substrate is disposed opposite and connected to the circuit board. The circuit board has a first opening facing the substrate and/or the substrate has a second opening facing the circuit board. The at least one passive component is disposed between the circuit board and the substrate and is at least partially accommodated in at least one of the first opening and the second opening.
    Type: Application
    Filed: October 25, 2021
    Publication date: June 23, 2022
    Inventor: Tung-Hsien HSIEH
  • Patent number: 11290571
    Abstract: A many-to-many state identification system of equipment names broadcasted from Internet-of-Things comprises IoT nodes and IoT mobile devices connecting the IoT nodes wirelessly. Each IoT node receives the sensed value of transducer on a machine element, determining whether the sensed value of transducer is abnormal. Next, the IoT node broadcasts an equipment identification name containing an existing gateway identification code and a state code of transducer showing whether the transducer is abnormal. When the IoT mobile device scans the equipment identification name broadcasted from the IoT node, a visual interface displays the state of IoT node by identifying the gateway identification code and the state code. Accordingly, before connecting the IoT mobile device to the IoT node, the state of transducer in the IoT node is acquired, allowing any IoT mobile device to monitor any transducer in a synchronous and many-to-many manner within the broadcasting area.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: March 29, 2022
    Assignee: NATIONAL FORMOSA UNIVERSITY
    Inventors: Wen-Yuh Jywe, Tung-Hsien Hsieh, Tung-hsing Hsieh, Yung-Chuan Huang, Ming-Sung Hsieh, Yung-Yi Huang
  • Publication number: 20210258402
    Abstract: A many-to-many state identification system of equipment names broadcasted from Internet-of-Things comprises IoT nodes and IoT mobile devices connecting the IoT nodes wirelessly. Each IoT node receives the sensed value of transducer on a machine element, determining whether the sensed value of transducer is abnormal. Next, the IoT node broadcasts an equipment identification name containing an existing gateway identification code and a state code of transducer showing whether the transducer is abnormal. When the IoT mobile device scans the equipment identification name broadcasted from the IoT node, a visual interface displays the state of IoT node by identifying the gateway identification code and the state code. Accordingly, before connecting the IoT mobile device to the IoT node, the state of transducer in the IoT node is acquired, allowing any IoT mobile device to monitor any transducer in a synchronous and many-to-many manner within the broadcasting area.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 19, 2021
    Inventors: Wen-Yuh JYWE, Tung-Hsien HSIEH, Tung-hsing HSIEH, Yung-Chuan HUANG, Ming-Sung HSIEH, Yung-Yi HUANG
  • Patent number: 10571259
    Abstract: An optical detecting apparatus for detecting a degree of freedom error of a spindle and has a standard bar and a sensor module, and is assembled between a spindle and a rotating platform of a powered machinery. The standard bar has a rod lens and a reflection face. The sensor module has two detecting groups, an oblique laser head, and a reflected spot displacement sensor. Each detecting group emits a laser light through the rod lens along the X-axis and the Y-axis of the powered machinery. The oblique laser head emits an oblique laser light to the reflected spot displacement sensor. When the spindle of the powered machinery generates errors after rotating, the sensor module receives the changes of the laser lights to obtain the displacement change signals of the standard bar for a calculation unit to detect the errors between the spindle and the rotating platform.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: February 25, 2020
    Assignee: National Formosa University
    Inventors: Wen-Yuh Jywe, Tung-Hsien Hsieh, Zhong-Liang Hsu, Chia-Ming Hsu, Yu-Wei Chang, Sen-Yi Huang, Tung-Hsing Hsieh
  • Patent number: 10224287
    Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.
    Type: Grant
    Filed: June 3, 2017
    Date of Patent: March 5, 2019
    Assignee: MediaTek Inc.
    Inventors: Shih-Yi Syu, Tung-Hsien Hsieh, Che-Ya Chou
  • Patent number: 10147674
    Abstract: Various structures of a semiconductor package assembly are provided. In one implementation, a semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer disposed on the die-attach surface, surrounding the semiconductor die. Further, a first conductive bump disposed over the first solder mask, coupled to a first pad of the redistribution layer (RDL) structure through a single circuit structure on a portion the first solder mask layer, wherein a first distance between a center of the first pad and a sidewall of the semiconductor die, which is close to the first pad, is equal to or greater than a second distance between a center of the first conductive bump and the sidewall of the semiconductor die.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 4, 2018
    Assignee: MediaTek Inc.
    Inventors: Tung-Hsien Hsieh, Che-Ya Chou
  • Publication number: 20180299263
    Abstract: An optical detecting apparatus for detecting a degree of freedom error of a spindle and has a standard bar and a sensor module, and is assembled between a spindle and a rotating platform of a powered machinery. The standard bar has a rod lens and a reflection face. The sensor module has two detecting groups, an oblique laser head, and a reflected spot displacement sensor. Each detecting group emits a laser light through the rod lens along the X-axis and the Y-axis of the powered machinery. The oblique laser head emits an oblique laser light to the reflected spot displacement sensor. When the spindle of the powered machinery generates errors after rotating, the sensor module receives the changes of the laser lights to obtain the displacement change signals of the standard bar for a calculation unit to detect the errors between the spindle and the rotating platform.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 18, 2018
    Inventors: Wen-Yuh Jywe, Tung-Hsien Hsieh, Zhong-Liang Hsu, Chia-Ming Hsu, Yu-Wei Chang, Sen-Yi Huang, Tung-Hsing Hsieh
  • Patent number: 10079192
    Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 18, 2018
    Assignee: MediaTek Inc.
    Inventors: Ching-Wen Hsiao, Tzu-Hung Lin, I-Hsuan Peng, Tung-Hsien Hsieh, Sheng-Ming Chang
  • Publication number: 20170271250
    Abstract: Various structures of a semiconductor package assembly are provided. In one implementation, a semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer disposed on the die-attach surface, surrounding the semiconductor die. Further, a first conductive bump disposed over the first solder mask, coupled to a first pad of the redistribution layer (RDL) structure through a single circuit structure on a portion the first solder mask layer, wherein a first distance between a center of the first pad and a sidewall of the semiconductor die, which is close to the first pad, is equal to or greater than a second distance between a center of the first conductive bump and the sidewall of the semiconductor die.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Tung-Hsien HSIEH, Che-Ya CHOU
  • Publication number: 20170271265
    Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.
    Type: Application
    Filed: June 3, 2017
    Publication date: September 21, 2017
    Inventors: Shih-Yi Syu, Tung-Hsien Hsieh, Che-Ya Chou
  • Patent number: 9704785
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die paddle. A supporting bar connects to the die paddle, extending in an outward direction from the die paddle. At least two power leads are separated from the die paddle and the supporting bar, having first terminals close to the die paddle and second terminals extending outward from the die paddle. A power bar connects to the at least two power leads, having a supporting portion. A molding material encapsulates the lead frame leaving the supporting portion exposed.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: July 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tung-Hsien Hsieh, Yi-Hui Lee
  • Patent number: 9704792
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer is disposed on the die-attach surface. The first solder mask layer surrounds the semiconductor die. An additional circuit structure is disposed on a portion of the first solder mask, surrounding the semiconductor die. The additional circuit structure includes a pad portion having a first width and a via portion has a second width that is less than the first width. The via portion passes through the first solder mask layer to be coupled the redistribution layer (RDL) structure.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tung-Hsien Hsieh, Che-Ya Chou
  • Patent number: 9704808
    Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: July 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Shih-Yi Syu, Tung-Hsien Hsieh, Che-Ya Chou
  • Publication number: 20160329262
    Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.
    Type: Application
    Filed: March 8, 2016
    Publication date: November 10, 2016
    Inventors: Ching-Wen Hsiao, Tzu-Hung Lin, I-Hsuan Peng, Tung-Hsien Hsieh, Sheng-Ming Chang
  • Publication number: 20160276277
    Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.
    Type: Application
    Filed: January 25, 2016
    Publication date: September 22, 2016
    Inventors: Shih-Yi Syu, Tung-Hsien Hsieh, Che-Ya Chou
  • Publication number: 20160260659
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer is disposed on the die-attach surface. The first solder mask layer surrounds the semiconductor die. An additional circuit structure is disposed on a portion of the first solder mask, surrounding the semiconductor die. The additional circuit structure includes a pad portion having a first width and a via portion has a second width that is less than the first width. The via portion passes through the first solder mask layer to be coupled the redistribution layer (RDL) structure.
    Type: Application
    Filed: February 19, 2016
    Publication date: September 8, 2016
    Inventors: Tung-Hsien HSIEH, Che-Ya CHOU
  • Publication number: 20160204053
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die peddle. A supporting bar connects to the die peddle, extending in an outward direction from the die peddle. At least two power leads are separated from the die peddle and the supporting bar, having first terminals close to the die peddle and second terminals extending outward from the die peddle. A power bar connects to the at least two power leads, having a supporting portion. A molding material encapsulates the lead frame leaving the supporting portion exposed.
    Type: Application
    Filed: September 22, 2015
    Publication date: July 14, 2016
    Inventors: Tung-Hsien HSIEH, Yi-Hui LEE
  • Patent number: 9331054
    Abstract: A semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 3, 2016
    Assignee: MEDIATEK INC.
    Inventors: Sheng-Ming Chang, Tung-Hsien Hsieh, Nan-Cheng Chen