Abstract: A semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.

Abstract: A method of numerical-control scraping of a work piece has a preparing step, a scanning step, a flatness-parameter inputting step, a surface-finishing step, a related-parameter inputting step, an auto-scraping step and an analyzing step. The preparing step comprises preparing a multi-axis machine tool, a laser displacement meter, an auto scraping apparatus and a computer. The scanning step comprises scanning the work piece. The flatness-parameter inputting step comprises inputting a flatness-parameter. The surface-finishing step comprises calculating out the to-be-scraped ranges of the work piece and scraping the work piece. The related-parameter inputting step comprises inputting desired PPI and POP in the computer, calculating out the HOP, the DOS and the oil content to obtain the length, the width and the depth of a single scraping process. The auto-scraping step comprises scraping the work piece to meet the requirement. The analyzing step comprises detecting the 3D-appearance drawing of the work piece.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.

Abstract: An exemplary flip-chip package is provided, including: a package structure having a first bonding pad and a second bonding pad formed thereon, wherein the first bond pad has a feature size different from a feature size of the second bond pad; a semiconductor chip facing the package structure, having a first under bump metal (UBM) layer and a second under bump metal (UBM) layer formed thereon, wherein the first UBM layer has a feature size different from a feature size of the second UBM layer; a first conductive element disposed between the first bond pad and the first UBM layer; and a second conductive element disposed between the second bond pad and the second UBM layer.

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a lower chip package; an upper chip package disposed on an upper surface of the lower chip package; at least one conducting element disposed between the lower chip package and the upper chip package; and at least one decoupling capacitor disposed on the upper surface of the lower chip package, wherein the decoupling capacitor is not covered by the upper chip package, and the decoupling capacitor is electrically connected to a power line or a ground line in the lower chip package.

Abstract: A method of numerical-control scraping of a work piece has a preparing step, a scanning step, a flatness-parameter inputting step, a surface-finishing step, a related-parameter inputting step, an auto-scraping step and an analyzing step. The preparing step comprises preparing a multi-axis machine tool, a laser displacement meter, an auto scraping apparatus and a computer. The scanning step comprises scanning the work piece. The flatness-parameter inputting step comprises inputting a flatness-parameter. The surface-finishing step comprises calculating out the to-be-scraped ranges of the work piece and scraping the work piece. The related-parameter inputting step comprises inputting desired PPI and POP in the computer, calculating out the HOP, the DOS and the oil content to obtain the length, the width and the depth of a single scraping process. The auto-scraping step comprises scraping the work piece to meet the requirement. The analyzing step comprises detecting the 3D-appearance drawing of the work piece.

Abstract: The invention provides a package structure, including: a substrate, wherein the substrate has a first surface and a second surface, and a first pattern metal layer is formed on the first surface, and a second patterned metal layer is formed on the second surface, and the substrate has a plurality of vias formed therein, wherein the first patterned metal layer is electrically connected to the second patterned metal layer through the plurality of vias, and the widths of the plurality of vias are gradually increased from the first surface to the second surface; a chip formed on the first surface of the substrate; and a molding material is formed on the substrate and the chip, wherein the chip is covered by the molding material.

Abstract: A semiconductor chip package is disclosed. The semiconductor chip package comprises a package substrate having a bottom surface. At least four adjacent ball pads are on the bottom surface, arranged in a first two-row array along a first direction and a second direction. At least four vias are drilled through the package substrate, arranged in a second two-row array, wherein each of the vias in a row of the second two-row array is offset by a first distance along the first direction and a second distance along the second direction from the connecting ball pads in a row of the first two-row array, and each of the vias in the other adjacent row of the second two-row array is offset by the first distance along an opposite direction to the first direction and the second distance along the second direction from the connecting ball pads in the other adjacent row of the first two-row array.

Abstract: This invention provides a semiconductor flip chip package including a carrier substrate and a flip chip mounted on the carrier substrate. The flip chip comprises a first input/output (I/O) pad and a second I/O pad on an active surface of the flip chip, wherein a switching between the first I/O pad and the second I/O pad is implemented by wire bonding.

Abstract: A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a trace interconnecting the intermediary terminal to the extended, outer terminal lead.

Abstract: A method for making a quad flat non-lead (QFN) semiconductor package includes half etching a first side of a carrier to form top portions of a lead array and a die attach surface of a die attach pad, wherein the lead array includes at least one inner terminal lead disposed adjacent to the die attach pad, at least one extended, outer terminal lead disposed along periphery of the QFN semiconductor package, and at least one intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead, wherein the intermediary terminal is disposed between the inner terminal lead and the extended, outer terminal lead.

Abstract: A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the extended, outer terminal lead.

Abstract: This invention provides a semiconductor flip chip package including a carrier substrate and a flip chip mounted on the carrier substrate. The flip chip comprises a first input/output (I/O) pad and a second I/O pad on an active surface of the flip chip, wherein a switching between the first I/O pad and the second I/O pad is implemented by wire bonding.

Abstract: A QFN package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an outer terminal lead; an intermediary terminal disposed between the inner terminal lead and the outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the outer terminal lead. A circuit board includes a core layer; a first metal trace disposed over a first side of the core layer; and a first solder mask covering the first metal trace. The QFN package is mounted over the first solder mask. No metal pad of the first metal trace is formed within an area corresponding to the intermediary terminal.

Abstract: A semiconductor chip package is disclosed. The semiconductor chip package comprises a package substrate having a bottom surface. At least four adjacent ball pads are on the bottom surface, arranged in a first two-row array along a first direction and a second direction. At least four vias are drilled through the package substrate, arranged in a second two-row array, wherein each of the vias in a row of the second two-row array is offset by a first distance along the first direction and a second distance along the second direction from the connecting ball pads in a row of the first two-row array, and each of the vias in the other adjacent row of the second two-row array is offset by the first distance along an opposite direction to the first direction and the second distance along the second direction from the connecting ball pads in the other adjacent row of the first two-row array.

Abstract: A semiconductor chip package is disclosed. The semiconductor chip package comprises a package substrate having a bottom surface. At least four adjacent ball pads are on the bottom surface, arranged in a first two-row array along a first direction and a second direction. At least four vias are drilled through the package substrate, arranged in a second two-row array, wherein each of the vias in a row of the second two-row array is offset by a first distance along the first direction and a second distance along the second direction from the connecting ball pads in a row of the first two-row array, and each of the vias in the other adjacent row of the second two-row array is offset by the first distance along an opposite direction to the first direction and the second distance along the second direction from the connecting ball pads in the other adjacent row of the first two-row array.

Abstract: A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the extended, outer terminal lead.

Abstract: A method for making a quad flat non-lead (QFN) semiconductor package includes half etching a first side of a carrier to form top portions of a lead array and a die attach surface of a die attach pad, wherein the lead array includes at least one inner terminal lead disposed adjacent to the die attach pad, at least one extended, outer terminal lead disposed along periphery of the QFN semiconductor package, and at least one intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead, wherein the intermediary terminal is disposed between the inner terminal lead and the extended, outer terminal lead.

Abstract: A semiconductor chip package includes a chip; first and second connection pads arranged in a matrix and disposed about the chip, and the first and second connection pads have different bottom surface shapes when viewed from a bottom of the QFN package; bonding pads provided on an active surface of the chip and being electrically connected with corresponding said connection pads through bonding wires; and a package body encapsulating the chip, the bonding wires and an upper portion of each of the connection pads such that a lower portion of each of the connection pads extends outward from a bottom of the package body.

Abstract: A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a trace interconnecting the intermediary terminal to the extended, outer terminal lead.