Abstract: The present invention relates to a method for limiting the current output by a speed controller (V) for three-phase asynchronous electric motor (M), said controller (V) operating according to a control law (LC) of pure U/F type. Said method is characterized in that it consists in calculating with the aid of a limitation function a correction value for the frequency of the stator (Wstat) then in applying thereto, so as to obtain, in the voltage control law (LC) of U/F type, a corrected frequency of the stator (Wstatc). According to the voltage control law of U/F type, the method thereafter consists on the basis of this corrected frequency of the stator (Wstatc) in obtaining the control voltage (Vqref) applied to the motor. The invention also relates to a system for limiting the current able to implement said method.

Abstract: The present invention refers to a method and to a system for managing the voltage (Vbus) of the DC bus of a speed controller for an AC electric motor (M) linked to a current distribution network (Rd). The method is characterized in that it consists in: comparing a value of the voltage (Vbus) measured on the DC bus with a determined limit value (Vlim), when the value of the voltage (Vbus) measured on the DC bus becomes greater than the limit value (Vlim), forcing the slope of an internal ramp (R) to a zero value so as to confer a constant frequency (Wstat) on the stator, when the value of the voltage (Vbus) measured on the DC bus again becomes less than the limit value (Vlim), progressively increasing the value of the slope of the internal ramp (R).

Abstract: A method for writing servo information onto a disk of a hard disk drive with a servo writer. The method includes writing a plurality of spiral servo signals with a head. The spiral servo signals are used to write servo patterns using at least one timing window. The timing window is adjusted using a position error signal generated from the spiral servo signals. The adjusted timing window is then used to write servo patterns onto the disk. Adjusting the timing window compensates for irregularities in the spiral servo signals.

Abstract: Read positioning method includes adjusting at least one read head position when accessing read track on at least one rotating disk surface based upon Burst Correction Value of nearest write track, when PES burst patterns of read track and nearest write track match. Apparatus supporting read positioning method may include means for at least partly performing each step. At least one means may include at least one instance of at least one of following: computer, finite state machine, neural network and inferential engine. At least one read method for the hard disk drive included. These read methods may be used during initialization and/or normal hard disk drive operation. Hard disk drive may include servo controller driving voice coil actuator and, preferably further driving micro-actuator. The hard disk drive may include more than one rotating disk surface and more than one rotating disk surface.

Abstract: The present invention is a method and apparatus for positioning a read/write head in a hard disk drive. The method comprises providing a disk having a at least one side with a plurality of tracks, where each of the tracks has a servo field with servo bits. The servo bits are read to provide a position signal for positioning a read/write head. The method determines a difference in position between an initial and a subsequent position of the read/write head on a track, where the subsequent location occurs after the read/write head has moved one revolution from the initial position on the track. The initial and subsequent positions are offset laterally. The method generates a compensation signal based on the initial position, the subsequent position and the difference. The position signal and the compensation signal are combined to provide a compensated position signal for positioning the read/write head. Various embodiments are described.

Abstract: The present invention is a method and apparatus for positioning a read/write head in a hard disk drive. The method comprises providing a disk having a at least one side with a plurality of tracks, where each of the tracks has a servo field with servo bits. The servo bits are read to provide a position signal for positioning a read/write head. The method determines a difference in position between an initial and a subsequent position of the read/write head on a track, where the subsequent location occurs after the read/write head has moved one revolution from the initial position on the track. The initial and subsequent positions are offset laterally. The method generates a compensation signal based on the initial position, the subsequent position and the difference. The position signal and the compensation signal are combined to provide a compensated position signal for positioning the read/write head. Various embodiments are described.

Abstract: Interfacing circuitry for asynchronously transferring data between a high-speed clock domain and a low-speed clock domain is provided. The interfacing circuitry is divided into halves, with one half being synchronized to a first clock and the second half being synchronized to a second clock. The first half and the second half are mirror images of each other. Each half has at least one storage component, such as a register and a flip-flop, for storing a valid bit as well as data, and at least one multiplexer component for gating the storage component. The valid bit is used to control the multiplexer at a receiving half. When transferring from a high-speed clock domain to a low-speed clock domain, the high-speed clock domain may probe the received data and/or the valid bit stored in the low-speed clock domain before the high-speed clock domain sends additional data.

Abstract: An interpenetrating polymer network (IPN) composition and a process for the manufacture of hydrogel contact lens using the invention material. The polymeric materials are formed by polymerization of: (1) an unsaturated alkyl(meth)acrylate or its derivatives such as 2-hydroxyethyl methacrylate as the principle monomer; (2) optionally vinyl containing comonomer(s) to enhance the resulting hydrogel water absorbing capability; (3) polymerizable multi-functional crosslinking agent(s); (4) an irradiation initiator and/or thermal initiator; (5) optionally other additives to impart the resulting hydrogel specific properties such as ultra-violet blocking ability and handling colors; in the presence of a soluble, hydrophilic IPN agent such as polyvinylpyrrolidone (PVP) or poly-2-ethyl-2-oxazoline (PEOX) with a specific molecular weight range.

Abstract: A method of mapping logical track numbers to a collection of physical tracks on at least two disk surfaces within a disk drive. The method further includes accessing logical tracks at assigned physical tracks. The invention includes making disk drives using the mapping of logical tracks to physical tracks and those disk drives as a product of that manufacturing process. The invention also includes program systems implementing the mapping of logical tracks to physical tracks within the disk drive and disk drives implementing the method of assigning logical tracks to physical tracks and/or accessing logical tracks based upon the physical track assignment.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a cache-flushing engine which allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the cache-flushing engine, a “flush” command is issued which forces the owner cache to write-back the dirty cache line to be flushed. Subsequently, a “flush request” is issued to the home memory of the memory block. The home node will acknowledge when the home memory is successfully updated. The cache-flushing engine operation will be interrupted when all flush requests are complete.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Abstract: Client-server software partitions Windows applications into multi-media and other less-observable instructions such that client may run audio/visual-related commands remotely, thereby appearing to client-user as when application were run solely by central server. Clients may access application through web-sites or remote access servers. Client requests may be atomized such that instruction set sub-sets are partitioned correspondingly. Operating system parameters on which application is run may be accessed selectably. Server may centralize client administration and provide metering of application usage.

Abstract: This client-server system partitions Windows applications into multi-media and other less-observable instructions such that client may run audio/visual-related commands remotely, thereby enabling an application appearance to client-user as when application were run solely by a single machine. Clients may access applications through web-sites or remote access servers. Client requests may be atomized such that instruction set sub-sets are partitioned correspondingly. Operating system parameters on which application is run may be accessed selectably. Server may centralize administration and provide metering of application usage.

Abstract: A method is provided for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the recall unit into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system.

Abstract: A system and method for processing multiple main memory accesses in parallel includes transmitting from the processor to the system control unit a first and a second transaction. These transactions are decoded to determine their corresponding commands and addresses. The system control unit includes a qualifier and a scheduler that assigns each transaction to a particular finite state machine (FSM). Each FSM executes a single transaction until completed. Each FSM machine maintains a record or keeps track of the state of progress of a transaction that is being executed by the system control unit. The FSMs keep track of the data by storing the data, such as the current state of the transaction, the status of the data, and an identifier describing which processor issued the transaction, for each transaction in a data buffer. The data value corresponding to a particular transaction may be retrieved from the main memory using a FSM.

Abstract: This invention relates to a system for limitation of the output current from a speed controller for three-phase asynchronous electric motors, comprising a PWM type converter in which the electronic switches are controlled by a microcontroller circuit (Mc), characterized by the fact that the microcontroller circuit comprises means (LIC) of calculating the modulus of the current vector using motor phase current measurements, and comparing it with a limitation set value in order to obtain a limitation error (y) and to calculate a correction voltage (&Dgr;V) that is added to the control voltage (V) applied to the motor.

Abstract: Systems and methods of processing network packets are described. These systems and methods provide improved packet processing results by logically and physically separating packet header processing functions from packet data processing functions. In this way, a network processing system may perform network handling operations and data processing operations substantially in parallel. One or more embodiments feature a network adapter for exchanging with a computer network information in the form of packets each including a packet header and packet data. The network adapter includes a packet parser configured to parse an information packet into a packet header and packet data and to direct the packet header to a first memory address for protocol processing and to direct packet data to a second memory address for data processing.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Abstract: Interfacing circuitry for asynchronously transferring data between a high-speed clock domain and a low-speed clock domain is provided. The interfacing circuitry is divided into halves, with one half being synchronized to a first clock and the second half being synchronized to a second clock. The first half and the second half are mirror images of each other. Each half has at least one storage component, such as a register and a flip-flop, for storing a valid bit as well as data, and at least one multiplexer component for gating the storage component. The valid bit is used to control the multiplexer at a receiving half. When transferring from a high-speed clock domain to a low-speed clock domain, the high-speed clock domain may probe the received data and/or the valid bit stored in the low-speed clock domain before the high-speed clock domain sends additional data.