Abstract: The present invention is a method and apparatus for positioning a read/write head in a hard disk drive. The method comprises providing a disk having a at least one side with a plurality of tracks, where each of the tracks has a servo field with servo bits. The servo bits are read to provide a position signal for positioning a read/write head. The method determines a difference in position between an initial and a subsequent position of the read/write head on a track, where the subsequent location occurs after the read/write head has moved one revolution from the initial position on the track. The initial and subsequent positions are offset laterally. The method generates a compensation signal based on the initial position, the subsequent position and the difference. The position signal and the compensation signal are combined to provide a compensated position signal for positioning the read/write head. Various embodiments are described.

Abstract: A computer system and method for enhancing memory-to-memory copy operations includes transmitting from the processor to the source system control unit a plurality of memory-to-memory copy transactions where each transaction includes a source address and a destination address. A lookup operation is performed on the destination address to determine the destination system control unit that controls access to the destination memory which contains the destination address. A number of data blocks located at the source address in the source memory are retrieved and transmitted to the destination address. The number of data blocks are stored at the destination address in the destination memory.

Abstract: A computer system and method for enhancing the reliability of a computer system by combining a cache sync-flush engine with a replicated memory module includes placing a “lock” command on the common bus. The lock protects or controls accesses to a number of memory locations in the memory modules designated by the programmer. At any point in time, one processor can obtain the lock, and hence has access to the number of memory locations protected by the lock. Other processors may attempt to acquire or make a request for the same lock, however, the other processor will fail until the processor that has the lock has released (i.e., “unlocked”) the lock. The other processors will keep trying to get the lock. The processor that obtains the lock instructs the system control unit to begin logging or monitoring all subsequent memory addresses that appear on the common bus.

Abstract: This invention relates to a system for limitation of the output current from a speed controller for three-phase asynchronous electric motors, comprising a PWM type converter in which the electronic switches are controlled by a microcontroller circuit (Mc), characterized by the fact that the microcontroller circuit comprises means (LIC) of calculating the modulus of the current vector using motor phase current measurements, and comparing it with a limitation set value in order to obtain a limitation error (y) and to calculate a correction voltage (&Dgr;V) that is added to the control voltage (V) applied to the motor.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

Abstract: A chromator for monitoring the end point of a plasma etching process is placed remotely from the window of a plasma etching chamber and is optically coupled to the window with a fiber optic cable bundle. The fiber optic cable bundle includes a first and a second bracket. Each bracket is specially designed to be compatible with existing chromator and plasma etching chambers. The first bracket, which attaches to the chamber, includes a plurality of slots for allowing the bracket to be axially and vertically adjusted to find the optimal optical point. Accordingly, the likelihood of the chromator properly detecting the end point is maximized. An inventive method a includes optically coupling the remotely located chromator by connecting a fiber optic cable bundle having a first bracket to the chamber, axially adjusting the bracket to find the optimal location for detecting the end point, and securing the first bracket to the chamber. The second bracket of the fiber optic cable bundle is connected to a chromator.

Abstract: An interpenetrating polymer network (IPN) composition and a process for the manufacture of hydrogel contact lens using the invention material. The polymeric materials are formed by polymerization of: (1) an unsaturated alkyl(meth)acrylate or its derivatives such as 2-hydroxyethyl methacrylate as the principle monomer; (2) optionally vinyl containing comonomer(s) to enhance the resulting hydrogel water absorbing capability; (3) polymerizable multi-functional crosslinking agent(s); (4) an irradiation initiator and/or thermal initiator; (5) optionally other additives to impart the resulting hydrogel specific properties such as ultra-violet blocking ability and handling colors; in the presence of a soluble, hydrophilic IPN agent such as polyvinylpyrrolidone (PVP) or poly-2-ethyl-2-oxazoline (PEOX) with a specific molecular weight range.

Abstract: A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A dielectric layer is then formed on the surface of the substrate, portions of which are then etched to define a channel opening for the device. A uniform nitride layer is formed over the surface of the substrate. The nitride layer is then etched to create nitride sidewall spacers. Additionally, the channel region is then etched to remove the doped portions of the active region. A gate dielectric is then formed, the gate dielectric including a nitrogen bearing oxide and a high K material. A gate conductor is then formed upon the high K material. A silicidation step is then performed. In alternative embodiments, the source/drain region is not formed and the source and drain are doped after the gate is complete. In the embodiment, the gate resides upon the active region and etching into the active region is not required.

Abstract: A frequency converter for an asynchronous motor including a voltage converter (O) equipped with switches (Sa, Sb, Sc) controlled by a control circuit (CC) and powered by a DC bus (B) on which a shunt (Sh) is installed to measure a DC current passing through the bus, wherein, when at least one of two components of an output voltage vector Vs is less than a predetermined value TMIN, the frequency converter includes a device which calculates firstly a vector Vs' each of two components thereof being at least equal to the predetermined value TMIN, and secondly a vector Vs" such that vectorial average of Vs' and Vs" is equal to the output vector Vs.